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Volumn 2001-January, Issue , 2001, Pages 384-389

ATPG for path delay faults without path enumeration

Author keywords

[No Author keywords available]

Indexed keywords

ATPG METHODOLOGY; FAULT COVERAGES; FUNCTIONAL TECHNIQUE; PATH DELAY FAULT; PATH ENUMERATION; PATH SENSITIZATION; TEST PATTERN; TEST SETS;

EID: 84949992220     PISSN: 19483287     EISSN: 19483295     Source Type: Journal    
DOI: 10.1109/ISQED.2001.915260     Document Type: Article
Times cited : (19)

References (14)
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  • 2
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  • 3
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    • Test generation for path delay faults based on satisfiability
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    • Cheng, C.-A.1    Gupta, S.K.2
  • 4
    • 0027833796 scopus 로고
    • Delay testing for non robust untestable circuits
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    • (1993) Proc. ITC , pp. 954-961
    • Cheng, K.-T.1    Chen, H.-C.2
  • 5
    • 0028714176 scopus 로고
    • BiTes: A BDD based test pattern generator for strong robust path delay faults
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  • 6
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    • RESIST: A recursive test pattern generation algorithm for path delay faults
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  • 7
    • 84939371489 scopus 로고
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    • C.J. Lin, and S.M. Reddy, "On delay fault testing in logic circuits", IEEE Trans. on CAD, pp. 694-703, Sept. 1987.
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    • Lin, C.J.1    Reddy, S.M.2
  • 9
    • 0032691216 scopus 로고    scopus 로고
    • A fast non-enumerative automatic test pattern generator for path delay faults
    • July
    • D. Karayiannis and S. Tragoudas, "A Fast Non-enumerative Automatic Test Pattern Generator for Path Delay Faults", IEEE Trans. on CAD, Vol. 18, No. 7, pp. 1050-1057, July 1999.
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  • 10
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    • Sept
    • W. Krunz and D.K. Pradhan, "Recursive Learning: A New Implication Technique for Efficient Solution of CAD Problems - Test, Verification, and Optimization", IEEE Trans. on CAD, Vol. 13, No. 9, pp. 1143-1158, Sept. 1994.
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  • 11
    • 0029547554 scopus 로고
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    • Dec
    • I. Pomeranz, S. M. Reddy and P. Uppaluri, "NEST: A Non-enumerative Test Generation Method for Path Delay Faults in Combinational Circuits", IEEE Trans. on CAD, Vol. 14, No. 12, pp. 1505-1515, Dec. 1995.
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  • 13
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  • 14
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.