Ubiquitous memory introspection

International Symposium on Code Generation and Optimization, CGO 2007

Volumn , Issue , 2007, Pages 299-311

  Zhao, Qin ^a,b   Rabbah, Rodric ^c   Amarasinghe, Saman ^a,d   Rudolph, Larry ^a,d   Wong, Weng Fai ^a,b  

^a SINGAPORE MIT ALLIANCE   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INSTRUCTION LEVEL FEEDBACK; MEMORY SYSTEM;

COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; ONLINE SYSTEMS; SOFTWARE PROTOTYPING;

UBIQUITOUS COMPUTING;

EID: 34547686261     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CGO.2007.12     Document Type: Conference Paper

References (25)

1. A. Agarwal, J. Hennessy, and M. Horowitz. An analytical cache model. ACM Trans. Comput. Syst., 7(2):184-215, 1989.
2. M. Arnold and B. G. Ryder. A framework for reducing the cost of instrumented code. In PLDI '01: Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation, pages 168-179, New York, NY, USA, 2001. ACM Press.
3. T. Austin. Pointer-intensive benchmark suite. http://www.cs.wisc.edu/ ~austin/ptr-dist.html.
4. K. Barr. Summarizing Multiprocessor Program Execution with Versatile, Microarchitecture-Independent Snapshots. PhD thesis, Massachusetts Institute of Technology, September 2006.
5. D. Bruening. Efficient, Transparent, and Comprehensive Runtime Code Manipulation. PhD thesis, Massachusetts Institute of Technology, September 2004. http://www.cag.csail.mit.edu/rio/.
6. D. Burger and T. Austin. The SimpleScalar Tool Set, Version 2.0. Technical report, University of Wisconsin-Madison Computer Science Department, 1997.
7. J. D. Collins, S. Sair, B. Calder, and D. M. Tullsen. Pointer cache assisted prefetching. In MICRO 35: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, pages 62-73, Los Alamitos, CA, USA, 2002. IEEE Computer Society Press.
8. J. D. Collins and D. M. Tullsen. Runtime identification of cache conflict misses: The adaptive miss buffer. ACM Trans. Comput. Syst., 19(4):413-439, 2001.
9. J. D. Collins, D. M. Tullsen, H. Wang, and J. P. Shen. Dynamic speculative precomputation. In MICRO 34: Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, pages 306-317, Washington, DC, USA, 2001. IEEE Computer Society.
10. J. D. Collins, H. Wang, D. M. Tullsen, C. Hughes, Y.-F. Lee, D. Lavery, and J. P. Shen. Speculative precomputation: long-range prefetching of delinquent loads. SIGARCH Comput. Archit. News, 29(2):14-25, 2001.
11. R. Cooksey, S. Jourdan, and D. Grunwald. A stateless, content-directed data prefetching mechanism. In ASPLOS-X: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, pages 279-290, New York, NY, USA, 2002. ACM Press.
12. J. Edler and M. Hill. Dinero IV Trace-Driven Uniprocessor Cache Simulator. http://www.es.wisc.edu/~markhill/DineroIV.
13. M. Hirzel and T. M. Chilimbi. Bursty tracing: A framework for low-overhead temporal profiling. In ACM Workshop on Feedback-Directed and Dynamic Optimization, 2001.
14. Intel Corporation. IA-32 Intel Architecture Optimization Reference Manual.
15. S. Laha, J. H. Patel, and R. K. IYER. Accurate low-cost methods for performance evaluation of cachememory systems. IEEE Transactions on Computers, 37(11):1325-1336, Nov 1988.
16. J. Lu, H. Chen, R. Fu, W.-C. Hsu, B. Othmer, P-C. Yew, and D.-Y Chen. The performance of runtime data cache prefetching in a dynamic optimization system. In MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, page 180, Washington, DC, USA, 2003. IEEE Computer Society.
17. J. Lu, A. Das, W.-C. Hsu, K. Nguyen, and S. G. Abraham. Dynamic helper threaded prefetching on the sun ultrasparc cmp processor. In MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, pages 93-104, Washington, DC, USA, 2005. IEEE Computer Society.
18. C-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: Building customized program analysis tools with dynamic instrumentation. In Programming Language Design and Implementation, pages 190-200, Chicago, IL, June 2005.
19. A. Moshovos, D. N. Pnevmatikatos, and A. Baniasadi. Sliceprocessors: an implementation of operation-based prediction. In ICS '01: Proceedings of the 15th international conference on Supercomputing, pages 321-334, New York, NY, USA, 2001. ACM Press.
20. N. Nethercote. Dynamic Binary Analysis and Instrumentation. PhD thesis, University of Cambridge, November 2004. http://valgrind.org/.
21. OLDEN benchmark suite. http://www.es.princeton.edu/~mcc/olden.html.
22. V.-M. Panait, A. Sasturkar, and W.-F. Wong. Static identification of delinquent loads. In CGO '04: Proceedings of the international symposium on Code generation and optimization, page 303, Washington, DC, USA, 2004. IEEE Computer Society.
23. PAPI: Performance application programmer interface. http://icl.cs.utk. edu/papi/.
24. Y. K. Toshihiro Ozawa and S. Nishizaki. Cache miss heuristics and preloading techniques for general-purpose programs. In Micro28: Proceedings of the 28th International Symposium on Microarchitecture, pages 243 - 248, 1995.
25. C. Zilles and G. Sohi. A programmable co-processor for profiling. In HPCA '01: Proceedings of International Symposium on High Performance Computer Architecture, 2001.