High-throughput memory-based architecture for DHT using a new convolutional formulation

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 7, 2007, Pages 606-610

  Meher, Pramod K ^a   Patra, Jagdish C ^a   Swamy, M N S ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b Gina Cody School of Engineering and Computer Science   (Canada)

Author keywords

Discrete Hartley transform (DHT); systolic array; VLSI

Indexed keywords

COMPUTATIONAL METHODS; MATHEMATICAL TRANSFORMATIONS; SYSTOLIC ARRAYS; VLSI CIRCUITS;

DISCRETE HARTLEY TRANSFORM; DISTRIBUTED ARITHMETIC-BASED IMPLEMENTATION;

CONVOLUTION;

EID: 34547579540     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.894407     Document Type: Article

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