An efficient systolic array algorithm for the VLSI implementation of a prime-length DHT

ISSCS 2005: International Symposium on Signals, Circuits and Systems - Proceedings

Volumn 1, Issue , 2005, Pages 167-169

  Chiper, D F ^a   Swamy, M N S ^b   Ahmad, M O ^b  

^a GHEORGHE ASACHI TECHNICAL UNIVERSITY OF IASI   (Romania)

^b Gina Cody School of Engineering and Computer Science   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION STRUCTURES; CYCLIC CONVOLUTIONS; INTERCONNECTION STRUCTURE; PRIME-LENGTH DHT;

ALGORITHMS; COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; SYSTOLIC ARRAYS; TOPOLOGY;

VLSI CIRCUITS;

EID: 33749065719     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCS.2005.1509879     Document Type: Conference Paper

References (10)

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