메뉴 건너뛰기




Volumn 2, Issue , 2003, Pages 567-570

An FPGA based parameterisable system for discrete Hartley transforms implementation

Author keywords

[No Author keywords available]

Indexed keywords

ACOUSTICS; ALGORITHMS; IMAGE ENHANCEMENT; MATHEMATICAL MODELS; MATHEMATICAL TRANSFORMATIONS; PARAMETER ESTIMATION; VECTORS;

EID: 0345566148     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (9)

References (13)
  • 1
    • 0025517054 scopus 로고
    • Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime-factor decomposition
    • Nov.
    • C. Chakrabarti and J. Ja'Ja', "Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime-factor decomposition." IEEE Trans. on Computers, Vol.39, pp. 1359-1368, Nov. 1990.
    • (1990) IEEE Trans. on Computers , vol.39 , pp. 1359-1368
    • Chakrabarti, C.1    Ja'Ja, J.2
  • 2
    • 0344436245 scopus 로고    scopus 로고
    • Prime factor decomposition of the discrete cosine transform and its hardware realisation
    • P.p.n. Yang and m.j. Narashimha, "prime factor decomposition of the discrete cosine transform and its hardware realisation." Proceedings Of The (ICASSP'85), PP.20.5.1-20.5.4.
    • Proceedings of the (ICASSP'85) , pp. 2051-2054
    • Yang, P.P.N.1    Narashimha, M.J.2
  • 3
    • 0032672345 scopus 로고    scopus 로고
    • High throughput vlsi implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier
    • Ss. Nayak., Pk. Meher, "High throughput vlsi implementation of discrete orthogonal transforms using bit-level vector-matrix multiplier." IEEE Trans.oncirc.& syst. Ii, analog and digital sig. Proc., vol.46, no.5, pp.655-658, 1999.
    • (1999) IEEE Trans. on Circ. & Syst. Ii, Analog and Digital Sig. Proc. , vol.46 , Issue.5 , pp. 655-658
    • Nayak, Ss.1    Meher, Pk.2
  • 6
    • 84948953898 scopus 로고    scopus 로고
    • An FPGA based Parametrisable System for Matrix Product Implementation
    • October 1-18, 20027
    • A. Amira and F. Bensaali "An FPGA based Parametrisable System for Matrix Product Implementation" Proceedings of The (SIPS2002), pp 75-79, October 1-18, 20027.
    • (2002) Proceedings of The (SIPS2002) , pp. 75-79
    • Amira, A.1    Bensaali, F.2
  • 7
    • 0345299387 scopus 로고    scopus 로고
    • URL: www.xilinx.com.
  • 8
    • 0029252869 scopus 로고
    • Design of Efficient Regular Arrays for Matrix Multiplication by Two-Step Regularization
    • Feb
    • J.Chuang and P.Y.Chang "Design of Efficient Regular Arrays for Matrix Multiplication by Two-Step Regularization" IEEE Transactions on Parallel and Distributed Systems Vol. 6, No.2, Feb 1995
    • (1995) IEEE Transactions on Parallel and Distributed Systems , vol.6 , Issue.2
    • Chuang, J.1    Chang, P.Y.2
  • 9
    • 0027576490 scopus 로고
    • A bit level systolic array for Walsh-Hadamard transforms
    • L.Chang and M.Chang Wu, "A bit level systolic array for Walsh-Hadamard transforms." Signal Processing Vol 31, pp 341-347, 1993.
    • (1993) Signal Processing , vol.31 , pp. 341-347
    • Chang, L.1    Chang Wu, M.2
  • 12
    • 0344868079 scopus 로고    scopus 로고
    • Mapping Full-Systolic Arrays for Matrix Product On Xilinx's XC4000
    • February, Monterey, CA, USA
    • A. Oudjida, S. Titri and M. Hamerlain "Mapping Full-Systolic Arrays for Matrix Product On Xilinx's XC4000." Proceedings of the FPGA2000, pp.222, February 2000, Monterey, CA, USA.
    • (2000) Proceedings of the FPGA2000 , pp. 222
    • Oudjida, A.1    Titri, S.2    Hamerlain, M.3
  • 13
    • 0345299386 scopus 로고    scopus 로고
    • URL: www.celoxica.com


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.