Scalable and modular memory-based systolic architectures for discrete Hartley transform

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 5, 2006, Pages 1065-1077

  Meher, Pramod Kumar ^a   Srikanthan, Thambipillai ^a   Patra, Jagdish C ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Dicrete Fourier transform (DFT); Discrete Hartley transform (DHT); Distributed arithmetic; ROM based architecture; Systolic arrays; VLSI

Indexed keywords

COMPUTATIONAL COMPLEXITY; DISCRETE FOURIER TRANSFORMS; RECURSIVE FUNCTIONS; ROM; VLSI CIRCUITS;

DISCRETE HARTLEY TRANSFORM (DHT); DISTRIBUTED ARITHMETIC; PRIME-FACTOR IMPLEMENTATION APPROACH;

SYSTOLIC ARRAYS;

EID: 33646578433     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.870225     Document Type: Article

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