Latency and power measurements on a 64-kb hybrid Josephson-CMOS memory

IEEE Transactions on Applied Superconductivity

Volumn 17, Issue 2, 2007, Pages 526-529

  Liu, Q ^a   Fujiwara, K ^a   Meng, X ^a   Whiteley, S R ^a   Van Duzer, T ^a   Yoshikawa, N ^b   Thakahashi, Y ^b   Hikida, T ^b   Kawai, N ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b YOKOHAMA NATIONAL UNIVERSITY   (Japan)

Author keywords

Access time; High speed measurement; Hybrid memory; Interface circuit

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ENERGY DISSIPATION; INTERFACES (MATERIALS); JOSEPHSON JUNCTION DEVICES; POWER AMPLIFIERS;

ACCESS TIME; HIGH-SPEED MEASUREMENT; HYBRID MEMORY; INTERFACE CIRCUIT;

CMOS INTEGRATED CIRCUITS;

EID: 34547534376     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2007.898698     Document Type: Conference Paper

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