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Volumn , Issue , 2006, Pages 121-130

A reconfigurable distributed computing fabric exploiting multilevel parallelism

Author keywords

[No Author keywords available]

Indexed keywords

CROSSBAR TECHNOLOGY; INTERCONNECTEFFICIENTS; MULTILEVEL PARALLELISM;

EID: 34547474639     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2006.15     Document Type: Conference Paper
Times cited : (6)

References (19)
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    • Hu, J.1    Marculescu, R.2
  • 3
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    • Storage-efficient, deadlockfree packet routing algorithms for torus netoworks
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    • (1994) IEEE Trans. Comput , vol.43 , Issue.12 , pp. 1376-1385
    • Cypher, R.1    Gravano, L.2
  • 5
    • 13944273381 scopus 로고    scopus 로고
    • An energy-efficient network-on-chip for a heterogeneous tiled reconfigurable systems-on-chip
    • Washington, DC, USA: IEEE Computer Society, pp
    • N. Kavaldjiev and G. J. M. Smit, "An energy-efficient network-on-chip for a heterogeneous tiled reconfigurable systems-on-chip," in DSD '04: Proceedings of the Digital System Design, EUROMICRO Systems on (DSD '04). Washington, DC, USA: IEEE Computer Society, pp. 492-498, 2004.
    • (2004) DSD '04: Proceedings of the Digital System Design, EUROMICRO Systems on (DSD '04) , pp. 492-498
    • Kavaldjiev, N.1    Smit, G.J.M.2
  • 7
    • 85143023349 scopus 로고    scopus 로고
    • L. Schweibert and D. N. Jayasimha, Optimal Fully Adaptive Wormhole Routing for Meshes, In Supercomputing '93, pp. 782-791, 1993.
    • L. Schweibert and D. N. Jayasimha, "Optimal Fully Adaptive Wormhole Routing for Meshes," In Supercomputing '93, pp. 782-791, 1993.
  • 8
    • 6344238665 scopus 로고    scopus 로고
    • Power Estimation Techniques for FPGAs
    • Oct
    • J. H. Anderson and F. N. Najm, "Power Estimation Techniques for FPGAs," IEEE Trans, on VLSI Syst., vol. 12, no. 10, pp. 1015-1027, Oct. 2004.
    • (2004) IEEE Trans, on VLSI Syst , vol.12 , Issue.10 , pp. 1015-1027
    • Anderson, J.H.1    Najm, F.N.2
  • 11
    • 0022920181 scopus 로고
    • The torus routing chip
    • Oct
    • W.J. Dally and C.L. Seitz, "The torus routing chip," in Journal of Dist. Computing, vol. 1, no. 3, pp. 187-196, Oct. 1986.
    • (1986) Journal of Dist. Computing , vol.1 , Issue.3 , pp. 187-196
    • Dally, W.J.1    Seitz, C.L.2
  • 13
    • 0034226899 scopus 로고    scopus 로고
    • The Odd-Even Turn Model for Adaptive Routing
    • G. M. Chiu, "The Odd-Even Turn Model for Adaptive Routing," in IEEE Tran. Parallel Distrib. Syst.., vol. 11, no. 7, pp. 729-73, 2000.
    • (2000) IEEE Tran. Parallel Distrib. Syst , vol.11 , Issue.7 , pp. 729-773
    • Chiu, G.M.1
  • 14
    • 84990479742 scopus 로고
    • An efficient heuristic procedure for partitioning graphs
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  • 15
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    • http://www.xilhix.com/hvdocs/userguides/ugQ-7Q.pdf. Virtex 4 User Guide vl .4 (UG070), Xilinx Inc., Sept. 2005.
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    • Altera Inc
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.