Advanced unbounded model checking based on AIGs, BDD sweeping, and quantifier scheduling

Proceedings of Formal Methods in Computer Aided Design, FMCAD 2006

Volumn , Issue , 2006, Pages 89-96

  Pigorsch, Florian ^a   Scholl, Christoph ^a   Disch, Stefan ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL MECHANICS; GRAPH THEORY; SCHEDULING ALGORITHMS; TEMPORAL LOGIC;

AND-INVERTER GRAPH (AIG); SYMBOLIC MODEL CHECKING; SYMBOLIC REPRESENTATIONS;

MODEL CHECKING;

EID: 34547463724     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FMCAD.2006.4     Document Type: Conference Paper

References (24)

1. A. Sistla and E. Clarke, "The complexity of propositional linear temporal logics," Journal of the ACM, vol. 32, no. 3, pp. 733-749, 1985.
2. E. Clarke, E. Emerson, and A. Sistla, "Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications," ACM Trans. on Programming Languages and Systems, vol. 8, no. 2, pp. 244-263, 1986.
3. 20 States and Beyond," Information and Computation, vol. 98(2), pp. 142-170, 1992.
4. K. McMillan, Symbolic Model Checking. Kluwer Academic Publisher, 1993.
5. R. Bryant, "Graph - based algorithms for Boolean function manipulation," IEEE Trans. on Camp., vol. 35, no. 8, pp. 677-691, 1986.
6. A. Biere, A. Cimatti, E. Clarke, and Y. Zhu, "Symbolic model checking without BDDs," in Tools and Algorithms for the Constuction and Analysis of Systems, ser. LNCS, vol. 1579. Springer Verlag, 1999.
7. A. Biere, A. Cimatti, E. Clarke, M. Fujita, and Y. Zhu, "Symbolic model checking using SAT procedures instead of BDDs," in Design Automation Conf., 1999.
8. M. Sheeran, S. Singh, and G. Stalmarck, "Checking Safety Properties Using Induction and a SAT-solver," in FMCAD, ser. LNCS, W. H. Jr. and S. Johnson, Eds., vol. 1954. Springer, 2000, pp. 407-420.
9. V. Paruthi and A. Kuehlmann, "Equivalence checking combining a structural SAT-solver, BDDs, and simulation," in Int'l Conf. on Comp. Design, 2000, pp. 459-464.
10. A. Kuehlmann, V. Paruthi, F. Krohm, and M. M.K. Ganai, "Robust Boolean Reasoning for Equivalence Checking and Functional Property Verification," IEEE Trans, on CAD, 2002.
11. A. Kuehlmann, "Dynamic transition relation simplification for bounded property checking," in Int'l Conf. on Computer-Aided Design, 2004, pp. 50-57.
12. A. Mishchenko, S. Chatterjee, R. Jiang, and R. Brayton, "FRAIGs: A unifying representation for logic synthesis and verification," EECS Dept., UC Berkeley, Tech. Rep., 03 2005.
13. P. Abdullah, P. Bjesse, and N. Een, "Symbolic reachability analysis based on sat-solvers," in Tools and Algorithms for the Constuction and Analysis of Systems, ser. LNCS, vol. 1785. Springer-Verlag, 2000.
14. P. Williams, A. Biere, E. Clarke, and A. Gupta, "Combining decision diagrams and SAT procedures for efficient symbolic model checking," in Computer Aided Verification, ser. LNCS, vol. 1855. Springer Verlag, 2000, pp. 124-138.
15. G. Cabodi, M. Crivellari, S. Nocco, and S. Quer, "Circuit based quantification: Back to state set manipulation with unbounded model checking," in Design, Automation and Test in Europe, 2005.
16. K. McMillan, "Applying SAT methods in unbounded symbolic model checking," in Computer Aided Verification, ser. LNCS, vol. 2404. Springer, 2002, pp. 250-264.
17. _, "Interpolation and SAT-Based Model Checking," in Computer Aided Verification ser. LNCS. Springer, 2003.
18. M. Ganai, A. Gupta, and P. Ashar, "Efficient SAT-based unbounded symbolic model checking using circuit cofactoring," in Int'l Conf. on Computer-Aided Design, 2004, pp. 510-517.
19. H.-J. Kang and I.-C. Park, "Sat-based unbounded symbolic model checking," IEEE Trans, on CAD, vol. 24, no. 2, pp. 129-140, February 2005.
20. A. Kuehlmann and F. Krohm, "Equivalence checking using cuts and heaps," in Design Automation Conf., 1997, pp. 263-268.
21. The VIS Group, "VIS Verification Benchmarks." [Online]. Available: http://vlsi.colorado.edu/~vis/
22. F. Pigorsch and C. Scholl, "Collection of benchmarks." [Online]. Available: http://www.informatik.uni-freiburg.de/~pigorsch/benchmarks. html
23. P. Bjesse and A. Boralv, "DAG-aware circuit compression for formal verification," in Int'l Conf. on CAD, 2004, pp. 42-49.
24. A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-aware AIG rewriting," in Design Automation Conf., 2006, pp. 532-535.