SAT-based unbounded symbolic model checking

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 2, 2005, Pages 129-140

  Kang, Hyeong Ju ^a   Park, In Cheol ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Boolean satisfiability checking (SAT); Formal verification; Symbol manipulation; Symbolic model checking

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; ERROR ANALYSIS; PATTERN RECOGNITION; PROBLEM SOLVING; SET THEORY;

BOOLEAN SATISFIABILITY CHECKING (SAT); FORMAL VERIFICATION; SYMBOL MANIPULATION; SYMBOLIC MODEL CHECKING;

MICROPROCESSOR CHIPS;

EID: 13144268611     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.841068     Document Type: Article

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