An all-digital pll with cascaded dynamic phase average loop for wide multiplication range applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4875-4878

  Chen, Pao Lung ^a,b   Chung, Ching Che ^a   Lee, Chen Yi ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b CHIN MIN INSTITUTE OF TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALL-DIGITAL PHASE LOCKED LOOP; ALL-DIGITAL PLL; CMOS PROCESS; DESIGN COMPLEXITY; DYNAMIC PHASE; FREQUENCY DETECTION; HIGH FREQUENCY LOOP; INPUT FREQUENCY; JITTER PERFORMANCE; LOOP CONTROL; LOOP STABILITY; LOW FREQUENCY; MULTIPLICATION FACTOR; PHASE ESTIMATORS; PROPOSED ARCHITECTURES;

JITTER; PHASE LOCKED LOOPS;

FREQUENCY ESTIMATION;

EID: 34547356018     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465725     Document Type: Conference Paper

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