A 3.0V 12b 120 MSample/s CMOS pipelined ADC

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 1023-1026

  Yoo, Sang Min ^a   Oh, Tae Hwan ^a   Lee, Ho Young ^a   Moon, Kyung Ho ^a   Kim, Jae Whui ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATORS (OPTICAL); MICROFABRICATION; NYQUIST DIAGRAMS; POWER AMPLIFIERS;

HIGH-SPEED OPERATION; TIMING SCHEMES;

CMOS INTEGRATED CIRCUITS;

EID: 34547341160     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. D. Kelly, W. Yang, L. Mehr, M. Sayuk, and L. Singer, "A 3V 340mW 14b 75MSPS ADC with 85dB SFDR at Nyquist," in ISSCC Dig. Tech. Papers, Feb. 2001, pp. 134-135.
2. H. Pan, M. Segami, M. choi, J. Cao, F. Halorl, and A. A. Abidi, "A 3.3V 12b 50MSample/s A/D converter in 0.6um CMOS with over 80dB SFDR," in JSSCC Dig. Tech. Papers, Feb. 2000, pp. 40-41.
3. A. Abo and P. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipelined Analog-to-Digital Converter," IEEE J. Solid-State Circuits, vol. 34. no. 5. pp. 599-606, May 1999.
4. S. M. Yoo, T. H. Oh, J. W. Moon, S. H. Lee, and U. K. Moon, "A 2.5V 10b 120Msample/s CMOS pipelined ADC with high SFDR," in Proc. Custom Integrated Circuits Conf., May 2002, pp. 441-444.
5. B. M. Min, P. Kim, D. Boisvert, and A. Aude, "A 69mW 10b 80MS/s pipelined CMOS ADC," in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 324-325.
6. O. Stroeble, V. Dias, and C. Sehwoerer, "An 80MHz 10b pipeline ADC with dynamic range doubling and dynamic reference selection," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 462-463.
7. K. Gulati et al., "A highly integrated analog baseband transceiver featuring a 12-bit 180MSPS pipelined A/D oonverter for multi-ohannel wireless LAN," in Symp. VLSI Circuits Dig. Tech. papers, June 2004, pp. 428-431.