A 69mW 10b 80MS/s pipelined CMOS ADC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Min, Byung Moo ^a   Kim, Peter ^a   Boisvert, David ^a   Aude, Arlo ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; BUFFER AMPLIFIERS; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; PIPELINE PROCESSING SYSTEMS; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE; TIMING DEVICES;

BOTTOM PLATE SAMPLING TECHNIQUE; COMPARATOR OFFSET VOLTAGE; DELAY CLOCK GENERATION; DIGITAL ERROR CORRECTION; DUAL GATE OXIDATION; FEEDBACK SIGNAL POLARITY INVERTING TECHNIQUE; POWER CONSUMPTION; TIMING DIAGRAMS;

CMOS INTEGRATED CIRCUITS;

EID: 0038645291     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. S. Kulhalli, V. Penkota, and R. Asv, "A 30mW 12b 21Msample/s Pipelined CMOS ADC," ISSCC Digest of Technical Papers, pp. 312-313, Feb. 2002.
2. K. Nagaraj, H. Fetterman, J. Anidjar, S. Lewis, and R. Renninger, "A 250-mW, 8-b, 52-Msamples/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers," IEEE J. Solid State Circuits, vol. 32, no. 3, pp. 312-320, March 1997.
3. P.C. Yu, and H.S. Lee, "2.5-V, 12-b, 5MS/s Pipelined CMOS ADC," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1854-1861, Dec. 1996.