-
1
-
-
28144436071
-
-
Masato Yoshioka, et al. A 10b 125MS/s 40mW Pipelined ADC in 0.18μm CMOS ISSCC 2005, Session 15, Paper 15.4, pp.282-283, Feb. 2005.
-
Masato Yoshioka, et al. "A 10b 125MS/s 40mW Pipelined ADC in 0.18μm CMOS" ISSCC 2005, Session 15, Paper 15.4, pp.282-283, Feb. 2005.
-
-
-
-
2
-
-
34547334056
-
-
Martin Clara, et al. A 1.8V Fully Embedded 10b 160MS/S Two-Step ADC in 0.18μm CMOS Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002 12-15 May 2002 Page(s):437 - 440
-
Martin Clara, et al. "A 1.8V Fully Embedded 10b 160MS/S Two-Step ADC in 0.18μm CMOS" Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002 12-15 May 2002 Page(s):437 - 440
-
-
-
-
3
-
-
34547262225
-
-
IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), 1596.3 SCI-LVDS Standard, IEEE Std 1596.3-1996, 1996.
-
"IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), 1596.3 SCI-LVDS Standard, IEEE Std 1596.3-1996, 1996.
-
-
-
-
4
-
-
0035309966
-
-
A.Boni, A.Pierazzi, D.Vecchi. LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS [J], IEEE J.Solid-state Circuits, 36, pp. 706-711.April 2001.
-
A.Boni, A.Pierazzi, D.Vecchi. "LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS" [J], IEEE J.Solid-state Circuits, vol.36, pp. 706-711.April 2001.
-
-
-
-
5
-
-
4344601199
-
-
Gunjan Mandal, et al. LOW Power LVDS Transmitter With Low Common Mode Variation For 1 Gb/s-per Pin Operation, in IEEE proc. ISCAS, vlo.1, pp. I1120-I1123, May 2004
-
Gunjan Mandal, et al. "LOW Power LVDS Transmitter With Low Common Mode Variation For 1 Gb/s-per Pin Operation," in IEEE proc. ISCAS, vlo.1, pp. I1120-I1123, May 2004
-
-
-
-
6
-
-
0037809963
-
-
Jaeseo Lee, et al. Design and Implementation of CMOS LVDS 2.5Gb/s Transmitter and 1.3Gb/s Receiver for Optical Interconnections, in IEEE Proc. ISCAS, 6,pp.702-705,May2001.
-
Jaeseo Lee, et al. "Design and Implementation of CMOS LVDS 2.5Gb/s Transmitter and 1.3Gb/s Receiver for Optical Interconnections," in IEEE Proc. ISCAS, vol 6,pp.702-705,May2001.
-
-
-
-
7
-
-
0035573395
-
A 622 MHz stand-alone LVDS driver pad in 0.18-μm CMOS Circuits and Systems, 2001
-
Shahriar Jamasb, et al., "A 622 MHz stand-alone LVDS driver pad in 0.18-μm CMOS" Circuits and Systems, 2001. MWSCAS 2001, vol.2, pp.610-613.
-
(2001)
MWSCAS
, vol.2
, pp. 610-613
-
-
Jamasb, S.1
-
8
-
-
13444306573
-
Low-Voltage Low-Power LVDS Drivers
-
February
-
Mingdeng Chen, et al., "Low-Voltage Low-Power LVDS Drivers," IEEE J. Solid-State Circuits, vol.40, N0.2, February 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
-
-
Chen, M.1
-
9
-
-
33847225942
-
Low Power LVDS Circuit for Serial Data Communications
-
Dec. 13-16, Hong Kong
-
Hwang-Cherng Chow,et al. "Low Power LVDS Circuit for Serial Data Communications" Processing of International Symposium, Dec. 13-16, 2005 Hong Kong.
-
(2005)
Processing of International Symposium
-
-
Chow, H.1
-
10
-
-
34547287904
-
-
IC 4.4.3 product documentation. San Jose, CA: Cadence Design Systems, Inc
-
"Transmission line model generator (LMG),"in IC 4.4.3 product documentation. San Jose, CA: Cadence Design Systems, Inc., 1999
-
(1999)
Transmission line model generator (LMG)
-
-
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