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Volumn , Issue , 2006, Pages 296-301

Buffer insertion in large circuits with constructive solution search techniques

Author keywords

Buffer insertion; Cost optimization; Interconnect synthesis; Physical design

Indexed keywords

COMBINATORIAL CIRCUITS; ITERATIVE METHODS;

EID: 34547289013     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146988     Document Type: Conference Paper
Times cited : (9)

References (12)
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  • 5
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    • Meeting delay constraints in DSM by minimal repeater insertion
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  • 7
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    • Efficient Algorithms for Buffer Insertion in General Circuits Based on Network Flow
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    • Alpert, C.J.1    Devgan, A.2
  • 9
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    • Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
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    • Shi, W.1    Li, Z.2    Alpert, C.J.3
  • 10
    • 34547259777 scopus 로고    scopus 로고
    • Path-based timing optimization by buffer insertion with accurate delay model
    • Oct
    • Y. Zhang, Q. Zhou, X. Hong and Y. Cai, "Path-based timing optimization by buffer insertion with accurate delay model", Proc. 5th International Conference on ASIC, Vol. 1:89-92, Oct. 2003.
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  • 11
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  • 12
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    • A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic
    • May
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.