A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 157-160

  Lee, Shuenn Yuh ^a   Chen, Chia Chyang ^a   Lee, Chyh Chyang ^a   Cheng, Chih Jen ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DATA STORAGE EQUIPMENT; ELECTRIC POWER UTILIZATION; FAST FOURIER TRANSFORMS; PROGRAM PROCESSORS; ROM;

CONTROL CIRCUITS; MEMORY CONTROL SCHEME; MIXED-RADIX ALGORITHM; SHARED-MEMORY ARCHITECTURE;

VLSI CIRCUITS;

EID: 34547288359     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. D. Cohen, "Simplified control of FFT hardware," IEEE Trans. Acoust., Speech, Signal Processing vol ASSP-24, pp. 577-579, Dec. 1976.
2. Y. Ma, "An effective memory addressing scheme for FFT processors," IEEE Trans. Signal Processing vol. 47, pp. 907-911, Mar. 1999.
3. Y. Ma and L. Wanhammar, "A hardware efficient control of memory addressing for high-performance FFT processors," IEEE Trans. Signal Processing vol. 48, No. 3, Mar. 2000.
4. L. G. Johnson, "Conflict free memory addressing for dedicated FFT hard ware," IEEE Trans. Circuits Syst. II, vol. 39, pp. 312-316, May 1992.
5. Lihong Jia: Yonghong Gao; Tenhunen, H.; "A pipelined shared-memory architecture for FFT processor," Midwest Symposium Circuits Syst. Vol. 39, pp. 804-807, Aug. 1999
6. Ching-Hsien Chang, Chin-Liang Wang, Member, IEEE, and Yu-Tai Chang, "Efficient VLSI Architectures for Fast Computation of the Discrete Fourier Transform and Its Inverse," IEEE Transactions of Signal Processing, vol. 48, No. 11, Nov. 2000.
7. Yutai Ma and Lars Wanhammar, "A Hardware Efficient Control of Memory Addressing for High-Performance FFT Processors," IEEE Transactions on Signal Processing, vol. 48, No.3, March 2000.
8. Yutai Ma, "An Effective Memory Addressing Scheme for FFT Processors," IEEE Transactions on Signal Processing, vol. 47, No.3, March 1999.