Pipelined shared-memory architecture for FFT processors

Midwest Symposium on Circuits and Systems

Volumn 2, Issue , 1999, Pages 804-807

  Jia, Lihong ^a   Gao, Yonghong ^a   Tenhunen, Hannu ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; ELECTRIC POWER SUPPLIES TO APPARATUS; FAST FOURIER TRANSFORMS; VLSI CIRCUITS;

POWER CONSUMPTION; PROCESS ELEMENTS; SHARED MEMORY ARCHITECTURE;

PIPELINE PROCESSING SYSTEMS;

EID: 0033292109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)