Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 478-483

  Hu, Yu ^a   Lin, Yan ^a   He, Lei ^a   Tuan, Tim ^b  

^a Engineering IV   (United States)

^b XILINX INC   (United States)

Author keywords

FPGA; Low power; Retiming

Indexed keywords

ELECTRIC POWER SYSTEM INTERCONNECTION; ENERGY DISSIPATION; ENERGY EFFICIENCY; LINEAR PROGRAMMING; POWER CONTROL; TIME DELAY;

INTERCONNECTS; TIME SLACK BUDGETING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34547219562     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147036     Document Type: Conference Paper

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