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Volumn , Issue , 2006, Pages 338-343

Verification of the cell broadband engine™ processor

Author keywords

Directed random verification; Hierarchical verification; Processor reference model; Trace based verification

Indexed keywords

BROADBAND NETWORKS; CELLULAR RADIO SYSTEMS; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; PROJECT MANAGEMENT;

EID: 34547201153     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146997     Document Type: Conference Paper
Times cited : (17)

References (10)
  • 1
    • 27344435504 scopus 로고    scopus 로고
    • The Design and Implementation of a First-Generation CELL Processor
    • February
    • D. Pham et al. The Design and Implementation of a First-Generation CELL Processor. In IEEE International SolidState Circuits Symposium, February 2005.
    • (2005) IEEE International SolidState Circuits Symposium
    • Pham, D.1
  • 2
    • 25844520697 scopus 로고    scopus 로고
    • The Microarchitecture of the Streaming Processor for a CELL Processor
    • February
    • B. Flachs et al. The Microarchitecture of the Streaming Processor for a CELL Processor. In IEEE International Solid-State Circuits Symposium, February 2005.
    • (2005) IEEE International Solid-State Circuits Symposium
    • Flachs, B.1
  • 3
    • 33748605840 scopus 로고    scopus 로고
    • An SPU Reference Model for Simulation, Random Test Generation, and Verification
    • January
    • Y. Watanabe et al. An SPU Reference Model for Simulation, Random Test Generation, and Verification. In IEEE Asia and South Pacific Design Automation Conference, January 2006.
    • (2006) IEEE Asia and South Pacific Design Automation Conference
    • Watanabe, Y.1
  • 4
    • 85165858321 scopus 로고    scopus 로고
    • www-128.ibm.com/developerworks/power/cell/
  • 7
    • 0036294466 scopus 로고    scopus 로고
    • Functional Verification of the POWER4 microprocessor and POWER4 multiprocessor system
    • Ludden et al. Functional Verification of the POWER4 microprocessor and POWER4 multiprocessor system. In IBM Journal of Research and Development, Volume 46, Number 1, 2002.
    • (2002) IBM Journal of Research and Development , vol.46 , Issue.1
    • Ludden1
  • 10
    • 0029230835 scopus 로고
    • Test Program Generation for Functional Verification of PowerPC Processors in IBM
    • Aharon et al. Test Program Generation for Functional Verification of PowerPC Processors in IBM. In Design Automation Conference (DAC), 1995.
    • (1995) Design Automation Conference (DAC)
    • Aharon1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.