An SPU reference model for simulation, random test generation and verification

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 860-866

  Watanabe, Yukio ^a   Sallay, Balazs ^b   Michael, Brad ^b   Brokenshire, Daniel ^b   Meil, Gavin ^b   Shafi, Hazim ^b   Hiraoka, Daisuke ^c  

^a TOSHIBA CORPORATION   (Japan)

^b IBM   (United States)

^c Sony Computer Entertainment Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; REDUCED INSTRUCTION SET COMPUTING; ROBUSTNESS (CONTROL SYSTEMS); SOFTWARE ENGINEERING;

INSTRUCTION SET ARCHITECTURE (ISA); RANDOM TEST CASE GENERATORS; SYNERGISTIC PROCESSING UNIT (SPU);

COMPUTER HARDWARE;

EID: 33748605840     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118495     Document Type: Conference Paper

References (4)

1. Pham D. et al, "The Design and Implementation of a First-eneration CELL Processor," 2005 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 184-185, Feb. 2005.
2. Flachs B. et al, "A streaming Processing Unit for a CELL Processor," 2005 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 134-135, Feb. 2005
3. Allon A. et al, "Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification," IEEE Design & Test of Computers 21(2): 84-93 (2004)
4. Patrick B. et al, "Mambo - A Full System Simulator for the PowerPC Architecture," ACM SIGMETRICS Performance Evaluation Review, 31(4): 8-12, Mar. 2004.