Power estimation starategies for a low-power security processor

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 367-371

  Lee, Yen Fong ^a   Huang, Shi Yu ^a   Hsu, Sheng Yu ^b   Chen, I Ling ^b   Shieh, Cheng Tan ^a   Lin, Jian Cheng ^a   Chang, Shih Chieh ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; CONSUMER BEHAVIOR; INTEGRATED CIRCUIT DESIGN; SPICE;

EVALUATION PLATFORMS; GATE LEVEL SIMULATION; LOW POWER SECURITY; PEAK POWER ESTIMATION; POTENTIAL PROBLEMS; POWER OPTIMIZATION; SECURITY PROCESSOR; VERIFICATION PROCESS;

HARDWARE SECURITY;

EID: 34547141220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120871     Document Type: Conference Paper

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