Captured-frame matching schemes for scalable input-queued packet switches

Computer Communications

Volumn 30, Issue 10, 2007, Pages 2149-2161

  Rojas Cessa, Roberto ^a   Lin, Chuan Bi ^a  

^a NEW JERSEY INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Captured frame; Frame eligibility; Input queued switch; Nonuniform traffic; Service frame

Indexed keywords

CAPTURED FRAMES; FRAME ELIGIBILITY; INPUT-QUEUED SWITCH; NONUNIFORM DISTRIBUTIONS; SERVICE FRAMES;

COMPUTATIONAL COMPLEXITY; ITERATIVE METHODS; PACKET NETWORKS; PHASE MATCHING; SCALABILITY; TELECOMMUNICATION TRAFFIC;

ROUTERS;

EID: 34447645655     PISSN: 01403664     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.comcom.2007.04.005     Document Type: Article

References (23)

1. Karol M., and Hluchyj M. Queuing in high-performance packet-switching. IEEE J. Sel. Area Commun. 6 (1988) 1587-1597
2. McKeown N., Mekkittikul A., Anantharam V., and Walrand J. Achieving 100% throughput in an input-queued switch. IEEE Trans. Commun. 47 (1999) 1260-1267
3. N. McKeown, Scheduling Algorithms for Input-Queued Cell Switches, Ph.D. Dissertation, Dept. Elect. Eng. Comput. Sci., University of California at Berkeley, Berkeley, CA, 1995.
4. Anderson T.E., Owicki S.S., Saxe J.B., and Tacker C.P. High-speed switch scheduling for local area networks. ACM Trans. Comput. Syst. 11 4 (1993) 319-352
5. McKeown N. The iSLIP scheduling algorithm for input-queued switches. IEEE/ACM Trans. Network. 7 4 (1999) 188-201
6. H.J. Chao, J.-S. Park, Centralized contention resolution schemes for a large-capacity optical ATM switch, IEEE ATM Workshop (1998) 11-16.
7. Oki E., Rojas-Cessa R., and Chao H.J. PMM: a pipelined maximal-sized matching scheduling approach for input-buffered switches. IEEE Globecom (2001) 35-39
8. Jiang Y., and Hamdi M. A fully desynchronized round-robin matching scheduler for a VOQ packet switch architecture. IEEE HPSR (2001) 407-411
9. Chang C.-S., Lee D.-S., and Jou Y.-S. Load balanced Birkhoff-Von Neumman switches. IEEE HPSR (2001) 276-280
10. Li Y., Panwar S., and Chao H.J. The dual round-robin matching switch with exhaustive service. IEEE HPSR (2002) 58-63
11. Tassiulas L. Linear complexity algorithms for maximum throughput in radio networks and input queued switches. IEEE INFOCOM 2 (1998) 533-539
12. Giaccone P., Prabhakar B., and Shah D. Randomized scheduling algorithms for high-aggregate bandwidth switches. IEEE J. Sel. Area Commun. 21 (2003) 546-559
13. Bianco A., Franceschinis M., Ghisolfi S., Hill A.M., Leonardi E., Neri F., and Webb R. Frame-based matching algorithms for input-queued switches. IEEE HPSR (2002) 69-76
14. Clos C. A study of nonblocking switching networks. Bell Syst. Tech. J. (1953) 406-424
15. Oki E., Jing Z., Rojas-Cessa R., and Chao H.J. Concurrent round-robin dispatching schemes for Clos-network switches. IEEE/ACM Trans. Network. 10 6 (2001) 830-844
16. Lee T.T., and Liew S.-Y. Parallel routing algorithm in Benes-Clos networks. IEEE INFOCOM' 96 (1996) 279-286
17. H.J. Chao, S.Y. Liew, Z. Jing, A dual-level matching algorithm for 3-stage Clos-network packet switches, in: Proc. 11th Symposium on High Performance Interconnects, (2003) 38-44.
18. Pun K., and Hamdi M. Static round-robin dispatching schemes for Clos-network switches. Proc. IEEE HPSR (2002) 239-243
19. Motoyama S., Petr D.W., and Frost V.S. Input-queued switch based on a scheduling algorithm. Electron. Lett. 31 14 (1995) 1127-1128
20. Nong G., Muppala J.K., and Hamdi M. Analysis of nonblocking ATM switches with multiple input queues, networking. IEEE/ACM Trans. Network. 7 1 (1999) 60-74
21. Rojas-Cessa R., Oki E., Jing Z., and Chao H.J. CIXB-1: combined input-one-cell-crosspoint buffered switch. IEEE HPSR (2001) 324-329
22. R. Schoene, G. Post, G. Sander, Weighted Arbitration Algorithms with Priorities for Input-Queued Switches with 100% Throughput, Broadband Switches Symposium'99, 1999. http://www.schoenen-service.de/assets/papers/Schoenen99bssw.pdf.
23. Chiussi F.M., Kneuer J.G., and Kumar V.P. Low-Cost Scalable Switching Solutions for Broadband Networking: the ATLANTA Architecture and Chipset. IEEE Commun. Mag. (1997) 44-53