Resource-efficient routing and scheduling of time-constrained network-on-chip communication

Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

Volumn , Issue , 2006, Pages 45-52

  Stuijk, Sander ^a   Basten, Twan ^a   Geilen, Marc ^a   Ghamarian, Amir Hossein ^a   Theelen, Bart ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; MULTIPROCESSING SYSTEMS; RESOURCE ALLOCATION; SCHEDULING;

NETWORK-ON-CHIP COMMUNICATION; RESOURCE UTILIZATION;

NETWORK ROUTING;

EID: 34347212751     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2006.81     Document Type: Conference Paper

References (17)

1. B. Ackland, et al. A single chip 1.6 billion 16-b MAC/s multiprocessor DSP. IEEE Journal of Solid-State Circuits, 35(3):412-124, 2000.
2. M. Bekooij, et al. Predictable multiprocessor system design. In SCOPES'04, Proc. pages 77-91. Springer, 2004.
3. L. Benini and G. de Micheli. Networks on chips: A new SoC paradigm. IEEE Comp., 35(1):70-78, 2002.
4. D. Culler, et al. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann, 1999.
5. W. Dally and B. Towles. Route packets, not wires: on-chip interconnection networks. In DAC'01, Proc., pages 684-689. ACM, 2001.
6. W. J. Dally and C. L. Seitz. The torus routing chip. Journal of distributed computing, 1(3): 187-196, 1986.
7. O. Gangwal, et al. Dynamic and Robust Streaming In and Between Connected Consumer-Electronics Devices, chapter Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the AEthereal Network on Chip, pages 1-36. Springer, 2005.
8. C. J. Glass and L. M. Ni. The turn model for adaptive routing. In Computer Architecture, Proc., pages 278-287, 1992.
9. K. Goossens, et al. A design flow for application-specific networks on chip with guaranteed performance to accelerate SoC design and verification. In DATE'05, Proc. pages 1182-1187. IEEE, 2005.
10. A. Hansson, et al. A unified approach to constrained mapping and routing on network-on-chip architectures. In CODES+ISSS, pages 75-80. IEEE, 2005.
11. J. Hu and R. Marculescu. Communication and task scheduling of application-specific networks-on-chip. IEE Proceedings: Computers and Digital Techniques, 152(5):643-651, 2005.
12. M. Millberg, et al. Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. In DATE'04, Proc., pages 890-895. IEEE.
13. S. Murali, et al. A methodology for mapping multiple use-cases onto networks on chip. In DATE'06, Proc., pages 118-123. IEEE, 2006.
14. P. Paulin, et al. Application of a multi-processor SoC platform to high-speed packet forwarding. In DATE'04, Proc., pages 58-63. IEEE, 2004.
15. E. Rijpkema, et al. Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. IEE Proceedings: Computers and Digital Techniques, 150(5):294-302, 2003.
16. A. Rǎdulescu, et al. An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. on CAD of ICs and systems, 24(1):4-17, 2005.
17. M. Rutten, et al. A heterogeneous multiprocessor architecture for flexible media processing. IEEE Design & Test of Computers, 19(4): 39-50, 2002.