Initial-on BSD protection design with PMO S-triggered SCR device

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Volumn , Issue , 2005, Pages 105-108

  Ker, Ming Dou ^a   Chen, Shih Hung ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTROSTATIC DISCHARGE; PROCESS MONITORING;

ESD PROTECTION; PMOS; PROTECTION DESIGN;

THYRISTORS;

EID: 34250768910     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2005.251818     Document Type: Conference Paper

References (6)

1. A. Chatterjec and T. Polgreen, "A low-voltage triggering SCR for on-chip BSD protection at output and input pads," IEEE Electron Device Letters, vol. 12, pp. 21-22,1991.
2. M.-D. Ker, H.-H. Chang, and C.-Y. Wu, "A gate-coupled PTLSCR/NTLSCR BSD protection circuit for deep-submicron low-voltage CMOS IC's," IEEEJ. Solid-State Circuits, vol. 32, pp. 38-51, 1997.
3. M.-D. Ker and K.-C. Hsu, "Latchup-free BSD protection design with complementary substrate-triggered SCR devices," IEEE J. Solid-State Circuits, vol. 38, pp. 1380-1392, 2003.
4. C. RUSS, J. Morgens, J. Armer, P. Jozwiak, G. Kolluri, and L. Avery, "GGSCR: GGNMOS triggered silicon controlled rectifiers for BSD protection in deep submicron CMOS processes," in Proc. of EOS/ESD Symp., 2001, pp. 22-31.
5. M.-D. Ker and K.-C. Hsu, "Native-NMOS-triggered SCR (NANSCR) for BSD protection in 0.13-μm CMOS integrated circuits," in Proc. of IEEE Int. Reliability Physics Symp., 2004, pp. 381-386.
6. M.-D. Ker, C.-Y. Chang, and H.-C. Jiang, "Design of negative charge pump circuit with polysilicon diodes in a 0.25-μm CMOS process," in Proc. of lEEEAP-ASIC Conf, 2002, pp. 145-148.