메뉴 건너뛰기




Volumn 26, Issue 7, 2007, Pages 1233-1245

Majority and minority network synthesis with application to QCA-, SET-, and TPL-based nanotechnologies

Author keywords

Design automation; Logic synthesis; Majority networks; Quantum cellular automata (QCA); Single electron tunneling (SET)

Indexed keywords

DESIGN AUTOMATION; LOGIC SYNTHESIS; QUANTUM CELLULAR AUTOMATA (QCA); SINGLE ELECTRON TUNNELING (SET);

EID: 34250745244     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.888267     Document Type: Article
Times cited : (49)

References (31)
  • 1
    • 34250713572 scopus 로고    scopus 로고
    • Semiconductor Industries Association Roadmap, Online, Available
    • Semiconductor Industries Association Roadmap. [Online], Available: http://public.itrs.net
  • 2
    • 36449009014 scopus 로고
    • Logical devices implemented using quantum cellular automata
    • Feb
    • P. D. Tougaw and C. S. Lent, "Logical devices implemented using quantum cellular automata," J. Appl. Phys., vol. 75, no. 3, pp. 1818-1825, Feb. 1994.
    • (1994) J. Appl. Phys , vol.75 , Issue.3 , pp. 1818-1825
    • Tougaw, P.D.1    Lent, C.S.2
  • 3
    • 0033713127 scopus 로고    scopus 로고
    • A design of and design tools for a novel quantum dot based microprocessor
    • Jun
    • M. T. Niemier, M. J. Kontz, and P. M. Kogge, "A design of and design tools for a novel quantum dot based microprocessor," in Proc. Des. Autom. Conf., Jun. 2000, pp. 227-232.
    • (2000) Proc. Des. Autom. Conf , pp. 227-232
    • Niemier, M.T.1    Kontz, M.J.2    Kogge, P.M.3
  • 4
    • 0033361573 scopus 로고    scopus 로고
    • A memory design in QCAs using the SQUARES formalism
    • Mar
    • D. Berzon and T. J. Fountain, "A memory design in QCAs using the SQUARES formalism," in Proc. ACM Great Lakes Symp. VLSI, Mar. 1999, pp. 166-169.
    • (1999) Proc. ACM Great Lakes Symp. VLSI , pp. 166-169
    • Berzon, D.1    Fountain, T.J.2
  • 5
    • 0037699755 scopus 로고    scopus 로고
    • Modeling QCA for area minimization in logic synthesis
    • Apr
    • N. Gergel, S. Craft, and J. Lach, "Modeling QCA for area minimization in logic synthesis," in Proc. ACM Great Lakes Symp. VLSI, Apr. 2003, pp. 60-63.
    • (2003) Proc. ACM Great Lakes Symp. VLSI , pp. 60-63
    • Gergel, N.1    Craft, S.2    Lach, J.3
  • 6
    • 0031123840 scopus 로고    scopus 로고
    • A device architecture for computing with quantum dots
    • Apr
    • C. S. Lent and P. D. Tougaw, "A device architecture for computing with quantum dots," Proc. IEEE, vol. 85, no. 4, pp. 541-557, Apr. 1997.
    • (1997) Proc. IEEE , vol.85 , Issue.4 , pp. 541-557
    • Lent, C.S.1    Tougaw, P.D.2
  • 7
    • 0034839133 scopus 로고    scopus 로고
    • Exploring and exploiting wire-level pipelining in emerging technologies
    • Jul
    • M. T. Niemier and P. M. Kogge, "Exploring and exploiting wire-level pipelining in emerging technologies," in Proc. Int. Symp. Comput. Architecture, Jul. 2001, pp. 166-177.
    • (2001) Proc. Int. Symp. Comput. Architecture , pp. 166-177
    • Niemier, M.T.1    Kogge, P.M.2
  • 8
    • 34250721304 scopus 로고    scopus 로고
    • Application-specific architecture for quantum cellular automata
    • Aug
    • F. Ciontu, C. Cucu, and B. Courtois, "Application-specific architecture for quantum cellular automata," in Proc. IEEE Int. Conf. Nanotechnol., Aug. 2002, pp. 351-354.
    • (2002) Proc. IEEE Int. Conf. Nanotechnol , pp. 351-354
    • Ciontu, F.1    Cucu, C.2    Courtois, B.3
  • 9
    • 0033358213 scopus 로고    scopus 로고
    • Logic in wire: Using quantum dots to implement a microprocessor
    • Mar
    • M. T. Niemier and P. M. Kogge, "Logic in wire: Using quantum dots to implement a microprocessor," in Proc. ACM Great Lakes Symp. VLSI, Mar. 1999, pp. 118-121.
    • (1999) Proc. ACM Great Lakes Symp. VLSI , pp. 118-121
    • Niemier, M.T.1    Kogge, P.M.2
  • 10
    • 2342652909 scopus 로고    scopus 로고
    • Incorporating standard CMOS design process methodologies into the QCA logic design process
    • Mar
    • S. C. Henderson, E. W. Johnson, J. R. Janulis, and P. D. Tougaw, "Incorporating standard CMOS design process methodologies into the QCA logic design process," IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 2-9, Mar. 2004.
    • (2004) IEEE Trans. Nanotechnol , vol.3 , Issue.1 , pp. 2-9
    • Henderson, S.C.1    Johnson, E.W.2    Janulis, J.R.3    Tougaw, P.D.4
  • 11
    • 77952376207 scopus 로고    scopus 로고
    • Complete logic family using tunnelingphase-logic devices
    • Nov
    • H. A. Fahmy and R. A. Kiehl, "Complete logic family using tunnelingphase-logic devices," in Proc. Int. Conf. Microelectron., Nov. 1999, pp. 22-24.
    • (1999) Proc. Int. Conf. Microelectron , pp. 22-24
    • Fahmy, H.A.1    Kiehl, R.A.2
  • 12
    • 2942713367 scopus 로고    scopus 로고
    • A majority-logic device using an irreversible single-electron box
    • Mar
    • T. Oya, T. Asai, T. Fukui, and Y. Amemiya, "A majority-logic device using an irreversible single-electron box," IEEE Trans. Nanotechnol., vol. 2, no. 1, pp. 15-22, Mar. 2003.
    • (2003) IEEE Trans. Nanotechnol , vol.2 , Issue.1 , pp. 15-22
    • Oya, T.1    Asai, T.2    Fukui, T.3    Amemiya, Y.4
  • 13
    • 0242591611 scopus 로고    scopus 로고
    • A majority-logic nanodevice using a balanced pair of single-electron boxes
    • Jun.-Aug
    • T. Oya, T. Asai, T. Fukui, and Y. Amemiya, "A majority-logic nanodevice using a balanced pair of single-electron boxes," J. Nanosci. Nanotech., vol. 2, no. 3/4, pp. 333-342, Jun.-Aug. 2002.
    • (2002) J. Nanosci. Nanotech , vol.2 , Issue.3-4 , pp. 333-342
    • Oya, T.1    Asai, T.2    Fukui, T.3    Amemiya, Y.4
  • 14
    • 34250778033 scopus 로고    scopus 로고
    • MALS, Online, Available
    • MALS. [Online]. Available: http://www.princeton.edu/-cad/projects. html
  • 15
    • 0034295896 scopus 로고    scopus 로고
    • Circuit/device modeling at the quantum level
    • Oct
    • Z. Yu, R. W. Dutton, and R. A. Kiehl, "Circuit/device modeling at the quantum level," IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1819-1825, Oct. 2000.
    • (2000) IEEE Trans. Electron Devices , vol.47 , Issue.10 , pp. 1819-1825
    • Yu, Z.1    Dutton, R.W.2    Kiehl, R.A.3
  • 20
    • 27944499984 scopus 로고
    • Majority logic synthesis by geometric methods
    • Feb
    • H. S. Miller and R. O. Winder, "Majority logic synthesis by geometric methods," IRE Trans. Electron. Comput., vol. EC-11, no. 1, pp. 89-90, Feb. 1962.
    • (1962) IRE Trans. Electron. Comput , vol.EC-11 , Issue.1 , pp. 89-90
    • Miller, H.S.1    Winder, R.O.2
  • 23
    • 10944245722 scopus 로고    scopus 로고
    • A method of majority logic reduction for quantum cellular automata
    • Dec
    • R. Zhang, K. Walus, W. Wang, and G. A. Jullien, "A method of majority logic reduction for quantum cellular automata," IEEE Trans. Nanotechnol., vol. 3, no. 4, pp. 443-450, Dec. 2004.
    • (2004) IEEE Trans. Nanotechnol , vol.3 , Issue.4 , pp. 443-450
    • Zhang, R.1    Walus, K.2    Wang, W.3    Jullien, G.A.4
  • 25
    • 0003101648 scopus 로고
    • Sequential circuit design using synthesis and optimization
    • Oct
    • E. M. Sentovich et al., "Sequential circuit design using synthesis and optimization," in Proc. Int. Conf. Comput. Des., Oct. 1992, pp. 328-333.
    • (1992) Proc. Int. Conf. Comput. Des , pp. 328-333
    • Sentovich, E.M.1
  • 26
    • 0035441521 scopus 로고    scopus 로고
    • Clocking of molecular quantum-dot cellular automata
    • Sep
    • K. Hennessy and C. S. Lent, "Clocking of molecular quantum-dot cellular automata," J. Vac. Sci. Technol., vol. 19, no. 5, pp. 1752-1755, Sep. 2001.
    • (2001) J. Vac. Sci. Technol , vol.19 , Issue.5 , pp. 1752-1755
    • Hennessy, K.1    Lent, C.S.2
  • 28
    • 2342457054 scopus 로고    scopus 로고
    • QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata
    • Mar
    • K. Walus, T. J. Dysart, G. A. Jullien, and R. A. Budiman, "QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata," IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 26-31, Mar. 2004.
    • (2004) IEEE Trans. Nanotechnol , vol.3 , Issue.1 , pp. 26-31
    • Walus, K.1    Dysart, T.J.2    Jullien, G.A.3    Budiman, R.A.4
  • 29
    • 34250774166 scopus 로고    scopus 로고
    • N. Kuwamura, K. Taniguchi, and C. Hamakawa, Simulation of single-electron logic circuits, IEICE Trans. Electron., J77-C-II, no. 5, pp. 221-228, 1994.
    • N. Kuwamura, K. Taniguchi, and C. Hamakawa, "Simulation of single-electron logic circuits," IEICE Trans. Electron., vol. J77-C-II, no. 5, pp. 221-228, 1994.
  • 30
    • 34250714588 scopus 로고    scopus 로고
    • MOSES, Online, Available
    • MOSES. [Online], Available: http://oriols.physics.sunysb.edu/set/ software/
  • 31
    • 0006480652 scopus 로고
    • Logic synthesis and optimization benchmarks
    • Center North Carolina, Research Triangle Park, NC, Tech. Rep
    • R. Lisanke, "Logic synthesis and optimization benchmarks," Microelectron. Center North Carolina, Research Triangle Park, NC, 1988. Tech. Rep.
    • (1988) Microelectron
    • Lisanke, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.