Incorporating Standard CMOS Design Process Methodologies into the QCA Logic Design Process

IEEE Transactions on Nanotechnology

Volumn 3, Issue 1 SPEC. ISS., 2004, Pages 2-9

  Henderson, Steven C ^a   Johnson, Eric W ^a   Janulis, Jason R ^a   Tougaw, P Douglas ^a  

^a VALPARAISO UNIVERSITY   (United States)

Author keywords

Design methodology; Hardware description language; Quantum dot cellular automata; Serial bit stream analyzer

Indexed keywords

AUTOMATA THEORY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MATHEMATICAL MODELS; QUANTUM THEORY; SEMICONDUCTOR QUANTUM DOTS;

AREA-MINIMIZATION TECHNIQUES; DESIGN METHODOLOGY; QUANTUM-DOT CELLULAR AUTOMATA; SERIAL BIT STREAM ANALYZER;

CMOS INTEGRATED CIRCUITS;

EID: 2342652909     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2003.820506     Document Type: Conference Paper

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