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Volumn , Issue , 2006, Pages 163-168

Study of design factors affecting turn-on time of silicon controlled rectifiers (SCRs) in 90 and 65NM bulk CMOS technologies

Author keywords

Electrostatic discharge (ESD); ESD protection circuits; Silicon Controlled Rectifier (SCR)

Indexed keywords

ELECTROSTATIC DISCHARGE (ESD); ESD PROTECTION CIRCUITS; SILICON CONTROLLED RECTIFIER (SCR);

EID: 34250693116     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2006.251210     Document Type: Conference Paper
Times cited : (58)

References (10)
  • 2
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    • Analysis of ESD Protection Components in 65nm CMOS Technology: Scaling Perspective and Impact on BSD Design Window
    • G. Boselli, J. Rodriguez, C. Duvury and J. Smith, "Analysis of ESD Protection Components in 65nm CMOS Technology: Scaling Perspective and Impact on BSD Design Window," Proc. EOS/ESD Symposium, pp. 43-52, 2005.
    • (2005) Proc. EOS/ESD Symposium , pp. 43-52
    • Boselli, G.1    Rodriguez, J.2    Duvury, C.3    Smith, J.4
  • 3
    • 23844554205 scopus 로고    scopus 로고
    • Overview of On-Chip Electrostatic Discharge Protection Design with SCR-Based Devices in CMOS Integrated Circuits
    • Jun
    • M.D. Ker and K.C. Hsu, "Overview of On-Chip Electrostatic Discharge Protection Design with SCR-Based Devices in CMOS Integrated Circuits," IEEE Transactions on Device and Materials Reliability, vol. 5, no. 2, pp. 235-249, Jun. 2005.
    • (2005) IEEE Transactions on Device and Materials Reliability , vol.5 , Issue.2 , pp. 235-249
    • Ker, M.D.1    Hsu, K.C.2
  • 4
    • 70449707416 scopus 로고    scopus 로고
    • Implementation of Diode and Bipolar Triggered SCRs for COM Robust ESD Protection in 90nm CMOS ASICS
    • C. Brennan, S. Chang, M. Woo, K. Chatty and R. Gauthier, "Implementation of Diode and Bipolar Triggered SCRs for COM Robust ESD Protection in 90nm CMOS ASICS," Proc. EOS/ESD Symposium, pp. 380-386, 2005.
    • (2005) Proc. EOS/ESD Symposium , pp. 380-386
    • Brennan, C.1    Chang, S.2    Woo, M.3    Chatty, K.4    Gauthier, R.5
  • 5
    • 77950787063 scopus 로고    scopus 로고
    • VF-TLP Systems Using TDT and TDRT for Kelvin Wafer Measurements and Package Level Testing
    • E. Grund and R. Gauthier, "VF-TLP Systems Using TDT and TDRT for Kelvin Wafer Measurements and Package Level Testing," Proc. EOS/ESD Symposium, pp. 338-345, 2004.
    • (2004) Proc. EOS/ESD Symposium , pp. 338-345
    • Grund, E.1    Gauthier, R.2
  • 7
    • 0033741133 scopus 로고    scopus 로고
    • Novel Diode-Chain Triggering SCR Circuits for ESD Protection
    • S.L. Jang, M.S. Gau and C.K. Lin, "Novel Diode-Chain Triggering SCR Circuits for ESD Protection," Solid-State Electronics, 44 (2000), pp. 1297-1303.
    • (2000) Solid-State Electronics , vol.44 , pp. 1297-1303
    • Jang, S.L.1    Gau, M.S.2    Lin, C.K.3
  • 8
    • 0842331348 scopus 로고    scopus 로고
    • Diode-Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGE HBTs and CMOS Ultra-Thin Gate Oxides
    • M. Mergens, C. Russ, K. Verhaege, J. Armer, P. Jozwiak, R. Mohn, B. Keppens and S. Trinh, "Diode-Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGE HBTs and CMOS Ultra-Thin Gate Oxides," IEDM, pp. 515-518, 2003.
    • (2003) IEDM , pp. 515-518
    • Mergens, M.1    Russ, C.2    Verhaege, K.3    Armer, J.4    Jozwiak, P.5    Mohn, R.6    Keppens, B.7    Trinh, S.8


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.