A low-power and high-quality implementation of the discrete cosine transformation

Advances in Radio Science

Volumn 5, Issue , 2007, Pages 305-311

  Heyne, B ^a   Gotze J ^a  

^a TU DORTMUND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COSINE TRANSFORMS; IMAGE CODING;

COMPUTATIONALLY EFFICIENT; CORDIC ALGORITHMS; DCT ALGORITHMS; DISCRETE COSINE TRANSFORMATION; HIGH QUALITY; HIGH-QUALITY IMPLEMENTATION; LOEFFLER DCT; SHIFT OPERATIONS;

DISCRETE COSINE TRANSFORMS;

EID: 34250616772     PISSN: 16849965     EISSN: 16849973     Source Type: Journal    
DOI: 10.5194/ars-5-305-2007     Document Type: Article

References (23)

1. The JPEG-6b Website, http://www.ijg.org/, 1998.
2. The XVID Website, http://www.xvid.oig/, 2005.
3. August, N. J. and Ha, D. S.: Low Power Design of DCT and IDCT for Low Bit Rate Video Codecs, IEEE Transactions on Multimedia, 6, 414-422, 2004.
4. Chen, W. H., Smith, C., and Fralick, S.: A Fast Computational Algorithm for the Discrete Cosine Transform, 25, 1004-1009, 1977.
5. Conzalez, R. C. and Woods, R. E.: Digial Image Processing, Prentice-Hall, Inc., New Jersey, 2001.
6. n DCT Algorithms Suitable for VLSI Implementation, in: IEEE International Conference on ICASSP, 12, 1805-1808, 1987.
7. Fanucci, L. and Saponara, S.: Data Driven VLSI Computation For Low-Power DCT-Based Video Coding, in: International Conf. on Electronics, Circuits and Systems, 541-544, 2002.
8. Goetze, J. and Hekstra, G.: An Algorithm and Architecture Based on Orthonormal Micro-Rotations for Computing the Symmetric EVD, in: Integration - The VLSI Journal, 20, 21-39, 1995.
9. Heyne, B. and Goetze, J.: A Pure Cordic Based FFT for Reconfigurable Digital Signal Processing, in: 12th European Signal Processing Conference, 2004.
10. Heyne, B., Buecker, M., and Goetze, J.: Implementation of a Cordic Based FFT on a Reconfigurable Hardware Accelerator, in: 3rd Karlsruhe Workshop on Software Radios, 2004.
11. Hsiao, S., Hu, Y., Juang, T., and Lee, C.: Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design, 52, 1568-1579, 2005.
12. Jeong, H., Kim, J., and Cho, W. K.: Low-Power Multiplierless DCT Architecture Using Image Correlation, 50, 262-267, 2004.
13. Li, J. and Lu, S. L.: Low Power Design of Two-Dimensional DCT, in: IEEE Conf. on ASIC and Exhibit, 309-312, 1996.
14. Loeffler, C., Lightenberg, A., and Moschytz, G. S.: Practical Fast 1-D DCT Algorithms With 11-Multiplications, in: Proc. ICASSP, 2, 988-991, Glasgow,UK, 1989.
15. Mariatos, E., Metafas, D., Hallas, J., and Goutis, C.: A Fast DCT Processor, Based on Special Purpose CORDIC Rotators, in: IEEE International Symposium on Circuits and Systems, 4, 271-274, 1994.
16. Richardson, I. E. G.: Video Codec Design, John Wiley & Sons Ltd, Atrium, England, 2002.
17. Shams, A., Pan, W., Chidanandan, A., and Bayoumi, M. A.: A Low-Power High Performance Distributed DCT Architecture, in: IEEE Computer Society Annual Symposium on VLSI, 21-27, 2002.
18. Sung, C. C., Ruan, S. J., Lin, B. Y., and Shie, M. C.: Quality and Power Effcient Architecture for the Discrete Cosine Transform, IEICE Transactions on Fundamentals Special Section on VLSI Design and CAD Algorithms, 2005.
19. Tran, T. D.: A Fast Multiplierless Block Transform for Image and Video Compression, in: International Conf. on Image Processing, 822-826, 1999.
20. Tran, T. D.: The BinDCT: Fast Multiplierless Approximation of the DCT, 7, 141-144, 2000.
21. Volder, J.: The CORDIC Trigonometric Computing Technique, IRE Trans. Electron. Comput, EC-8, 330-334, 1959.
22. Walther, J.: A Unified Algorithm for Elementary Functions, in: Proc. Spring Joint Comput. Conf., 38, 379-385, 1971.
23. Wang, Z.: Fast Algorithms for the Discrete W Transform and for the Discrete Fourier Transform, 32, 803-816, 1984.