A low power high performance distributed DCT architecture

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2002-January, Issue , 2002, Pages 26-32

  Shams, A ^b   Pan, W ^a   Chidanandan, A ^a   Bayoumi, M A ^a  

^a University of Louisiana at Lafayette   (United States)

^b NONE   (United States)

Author keywords

Arithmetic; Computer architecture; Digital signal processing; Digital signal processing chips; Discrete cosine transforms; Distributed computing; Hardware; High performance computing; Read only memory; Very large scale integration

Indexed keywords

COMPUTER HARDWARE; COSINE TRANSFORMS; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; DISCRETE COSINE TRANSFORMS; DISTRIBUTED COMPUTER SYSTEMS; FILTER BANKS; ROM; SIGNAL PROCESSING; VLSI CIRCUITS;

ADDER ARRAYS; DIGITAL SIGNAL PROCESSING CHIPS; DISTRIBUTED ARITHMETIC; DSP ARCHITECTURES; HIGH PERFORMANCE COMPUTING; INNER PRODUCT; LOW POWER PERFORMANCE; OPTIMIZED ARCHITECTURES;

COMPUTER ARCHITECTURE;

EID: 84948672235     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2002.1016869     Document Type: Conference Paper

References (24)

1. A.Peled, B.Liu, "A new hardware realization of digital filters," IEEE Trans. ASSP, vol.ASSP-22,no.6, pp.456-462, Dec.1974.
2. D.F.Elliott (ed.), Handbook of Digital Signal Processing, Academic Press, pp.964-972, 1987.
3. S.A.White, "Applications of distributed arithmetic to digital signal processing: A tutorial review," IEEE ASSP Magazine, pp.4-19, July 1989.
4. G-K.Ma and F.J.Taylor, "Multiplier policies for digital signal processing," IEEE ASSP Magazine, pp.6-19, Jan.1990.
5. M. T. Sun, L. Wu, and M. L. Liou, "A concurrent architecture for VLSI implementation of discrete cosine transform," IEEE Trans. Circuits Syst., vol. CAS-34, pp.992-994, Aug. 1987.
6. M.T.Sun, T.C.Chen, and A.M.Gottlieb, "VLSI implementation of a 16x 16 discrete cosine transform," IEEE Trans. Circuits Syst., vol. CAS-36, no.4, pp.610-617, April 1989.
7. S. Uramoto, Y. Inoue, A. Takabatake, J. Takeda, Y. Yamashita, H. Terane, and M. Yoshimoto, "A 100-MHz 2-D discrete cosine transform core processor," IEEE J. Solid-State Circuits, vol.27, pp. 492-498, April 1992 .
8. H. Fujiwara, M. L. Liou, M. T. Sun, K. M. Yang, M. Maruyama, K. Shomura, K. Ohyama, "An all-ASIC implementation of a low bit-rate video codec," IEEE Trans. Circuits Syst. Video Technol., vol.2, pp.123-133, June 1992.
9. Y-H.Chan and W-C.Siu, "On the realization of discrete cosine transform using the distributed arithmetic," IEEE trans. on Circuits and Systems - 1:Fundamental Theory and Applications, vol.39, no.9, pp.705-711, Sep.1992
10. H.C.Karthanasis,"A low ROM distributed arithmetic implementation of the forward/inverse DCT/DST using rotations,"IEEE trans. on Consumer Electronics, vol.41, no.2 , May 1995, pp.263-272.
11. T.Masake, et.al., "VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding," IEEE Trans. Circuits Syst. Video Technol., vol.5, no.5, pp.387-393, Oct 1995.
12. T. Kuroda et al., "a 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme," IEEE Journal of Solid State Circuits, vol.31, no.11, Nov.1996, pp.1770-1777.
13. K.R.Rao and P.Yip, Discrete Cosine Transform - Algorithms, Advantages, Applications, Academic Press, Inc. London, 1990.
14. A.Chatterjee, R.K.Roy, and M.A.d'Abreu, "Greedy hardware optimization for digital circuits using number splitting and refactorization," IEEE Trans. VLSI Systems, vol.1, no.4, Dec. 1993, pp.423-431.
15. M.Potkonjak, M.B.Srivastava and A.P.Chandrakasan, "Multiple constant multiplications: efficient and versatile framework and algorithms for exploring subexpression elimination," IEEE Trans. Computer-Aided Design, vol.15, no.2, Feb. 1996, pp.151-165.
16. P. A. Ruetz, P. Tong, D. Bailey, D. A. Luthi, and P. H. Ang, "A high performance full-motion video compression chip set," IEEE Trans. Circuits Syst. Video Technol., vol.2,pp.111-121, June 1992.
17. V.Srinivasan and K.J.R.Liu, "VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications," IEEE Trans. Circuits Syst. Video Technol., vol.6, no.1, pp.87-96,Feb. 1996.
18. CCITT Recommendation H.261, 1990 (Annex 1).
19. D. Slawecki and W. Li, "DCT/IDCT processor design for high data rate image code,"IEEE Trans. Circuits Syst. Video Technol., vol.2, pp.135-144, June 1992.
20. A. Madisetti and A. N. Willson, "A 100 MHz 2-D 8 x 8 DCT/IDCT processor for HDTV application," IEEE Trans. Circuits Syst. Video Technol., vol.5, pp.158-164, April 1995.
21. D.J.LeGall, "MPEG: A video compression standard for multimedia applications," Communications, ACM, 34, 4, Apr.1991.
22. G.Wallace, "The JPEG still picture compression standard." Communications, ACM, 34, 4, Apr.1991.
23. Homepage of 4i2i Communications Ltd, Aberdeen, Scotland, UK, Nov.1997.
24. S. Yu, E.E. Swartzlander Jr., '"DCT Implementation with Distributed Arithmetic," IEEE Transactions on Computers, vol.50, pp.985-991, Sept. 2001.