-
2
-
-
0032256392
-
Implementation of a fast H.263+ encoder/decoder
-
Sept.
-
B. Erol, F. Kossentini, and H. Alnuweiri, "Implementation of a fast H.263+ encoder/decoder," in Conf. Rec. Thirty-Second Asilomar Conference on Signals, Systems & Computers, vol. 1, Sept. 1998, pp. 462-466.
-
(1998)
Conf. Rec. Thirty-second Asilomar Conference on Signals, Systems & Computers
, vol.1
, pp. 462-466
-
-
Erol, B.1
Kossentini, F.2
Alnuweiri, H.3
-
3
-
-
0017538003
-
A fast computational algorithm for the discrete cosine transform
-
Sep.
-
W. H. Chen, C. H. Smith, and S. C. Fralick, "A fast computational algorithm for the discrete cosine transform," IEEE Trans. Commun., vol. COM-25, pp. 1004-1009, Sep. 1977.
-
(1977)
IEEE Trans. Commun.
, vol.COM-25
, pp. 1004-1009
-
-
Chen, W.H.1
Smith, C.H.2
Fralick, S.C.3
-
4
-
-
0021619710
-
A new algorithm to compute the discrete cosine transform
-
Dec.
-
B. G. Lee, "A new algorithm to compute the discrete cosine transform," IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-32, pp. 1243-1245, Dec. 1984.
-
(1984)
IEEE Trans. Acoust., Speech, Signal Processing
, vol.ASSP-32
, pp. 1243-1245
-
-
Lee, B.G.1
-
5
-
-
0026130969
-
Fast algorithm and implementation of 2-D discrete cosine transform
-
Mar.
-
N. I. Cho and S. U. Lee, "Fast algorithm and implementation of 2-D discrete cosine transform," IEEE Trans. Circuits Syst., vol. 38, pp. 297-305, Mar. 1991.
-
(1991)
IEEE Trans. Circuits Syst.
, vol.38
, pp. 297-305
-
-
Cho, N.I.1
Lee, S.U.2
-
6
-
-
0002911161
-
A cost-efficient and fully-pipelinable architecture for DCT/IDCT
-
Aug.
-
S.-F. Hsiao, W.-R. Shiue, and J.-M. Tseng, "A cost-efficient and fully-pipelinable architecture for DCT/IDCT," IEEE Trans. Consumer Electron., vol. 45, pp. 515-525, Aug. 1999.
-
(1999)
IEEE Trans. Consumer Electron.
, vol.45
, pp. 515-525
-
-
Hsiao, S.-F.1
Shiue, W.-R.2
Tseng, J.-M.3
-
7
-
-
0032664920
-
An area efficient DCT architecture for MPEG-2 video encoder
-
Feb.
-
K. Kim and J.-S. Koh, "An area efficient DCT architecture for MPEG-2 video encoder," IEEE Trans. Consumer Electron., vol. 45, pp. 62-67, Feb. 1999.
-
(1999)
IEEE Trans. Consumer Electron.
, vol.45
, pp. 62-67
-
-
Kim, K.1
Koh, J.-S.2
-
8
-
-
0029292227
-
A 100 MHz 2-D 8 × 8 DCT/IDCT processor for HDTV applications
-
Apr.
-
A. Madisetti and A. N. Willson, Jr., "A 100 MHz 2-D 8 × 8 DCT/IDCT processor for HDTV applications," IEEE Trans. Circuits Systems Video Technol., vol. 5, pp. 158-165, Apr. 1995.
-
(1995)
IEEE Trans. Circuits Systems Video Technol.
, vol.5
, pp. 158-165
-
-
Madisetti, A.1
Willson Jr., A.N.2
-
9
-
-
0009934403
-
A design of 2-D DCT/IDCT for real-time video applications
-
Oct.
-
I.-K. Kim, J.-J. Cha, and H.-J. Cho, "A design of 2-D DCT/IDCT for real-time video applications," in P roc. 6th Int. Conf. VLSI and CAD, Oct. 1999, pp. 557-559.
-
(1999)
Proc. 6th Int. Conf. VLSI and CAD
, pp. 557-559
-
-
Kim, I.-K.1
Cha, J.-J.2
Cho, H.-J.3
-
10
-
-
0031653271
-
A power efficient implementation of the discrete cosine transformation
-
Nov.
-
C. V. Schimpfle, P. Rieder, and J. A. Nossek, "A power efficient implementation of the discrete cosine transformation," in Conf. Rec. Thirty-First Asilomar Conference on Signals, Systems & Computers, vol. 1, Nov. 1997, pp. 729-733.
-
(1997)
Conf. Rec. Thirty-first Asilomar Conference on Signals, Systems & Computers
, vol.1
, pp. 729-733
-
-
Schimpfle, C.V.1
Rieder, P.2
Nossek, J.A.3
-
11
-
-
0000194406
-
A low power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization
-
May
-
T. Xanthopoulos and A. P. Chandrakasan, "A low power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization," IEEE J. Solid State Cricuits, vol. 35, pp. 740-750, May 2000.
-
(2000)
IEEE J. Solid State Cricuits
, vol.35
, pp. 740-750
-
-
Xanthopoulos, T.1
Chandrakasan, A.P.2
-
12
-
-
0028481156
-
A 0.8μ 100 MHz 2-D DCT core processor
-
Aug.
-
Y.-F. Jang, J.-N. Kao, J.-S. Yang, and P.-C. Huang, "A 0.8μ 100 MHz 2-D DCT core processor," IEEE Trans. Consumer Electron., vol. 40, pp. 703-710, Aug. 1994.
-
(1994)
IEEE Trans. Consumer Electron.
, vol.40
, pp. 703-710
-
-
Jang, Y.-F.1
Kao, J.-N.2
Yang, J.-S.3
Huang, P.-C.4
-
14
-
-
0003048785
-
-
Ph.D. dissertation, EE Dept., Virginia Polytech. Inst. State Univ., Blacksburg
-
H. B. Kim, "High-Level Synthesis and Implementation of Built-in Self-Testable Data Path Intensive Circuit," Ph.D. dissertation, EE Dept., Virginia Polytech. Inst. State Univ., Blacksburg, 1999.
-
(1999)
High-level Synthesis and Implementation of Built-in Self-testable Data Path Intensive Circuit
-
-
Kim, H.B.1
-
15
-
-
0026925543
-
Fast algorithms for the discrete cosine transform
-
Sept.
-
E. Feig and S. Winograd, "Fast algorithms for the discrete cosine transform," IEEE Trans. Signal Processing, vol. 40, pp. 2174-2193, Sept. 1992.
-
(1992)
IEEE Trans. Signal Processing
, vol.40
, pp. 2174-2193
-
-
Feig, E.1
Winograd, S.2
-
16
-
-
0028996584
-
A 2-D DCT low-power architecture for H.261 coders
-
May
-
E. Scopa, A. Leone, R. Guerreiri, and G. Baccarani, "A 2-D DCT low-power architecture for H.261 coders," in Proc. 1995 ICASSP, vol. 5, May 1995, pp. 3271-3274.
-
(1995)
Proc. 1995 ICASSP
, vol.5
, pp. 3271-3274
-
-
Scopa, E.1
Leone, A.2
Guerreiri, R.3
Baccarani, G.4
-
17
-
-
0031168228
-
A cost-effective architecture for 8 × 8 two-dimensional DCT/IDCT using direct method
-
June
-
Y.-P. Lee, T.-H. Chen, L.-G. Chen, M.-J. Chen, and C.-W. Ku, "A cost-effective architecture for 8 × 8 two-dimensional DCT/IDCT using direct method," IEEE Trans. Circuits Syst. Video Technol., vol. 7, pp. 459-467, June 1997.
-
(1997)
IEEE Trans. Circuits Syst. Video Technol.
, vol.7
, pp. 459-467
-
-
Lee, Y.-P.1
Chen, T.-H.2
Chen, L.-G.3
Chen, M.-J.4
Ku, C.-W.5
-
18
-
-
0032218694
-
A low power 2-D DCT chip design using direct 2-D algorithm
-
Feb.
-
L.-G. Chen, J.-Y. Jiu, H.-C. Chang, Y.-P. Lee, and C.-W. Ku, "A low power 2-D DCT chip design using direct 2-D algorithm," in Proc. ASP-DAC '98. Asia and South Pacific Design Automation Conf., Feb. 1998, pp. 145-150.
-
(1998)
Proc. ASP-DAC '98. Asia and South Pacific Design Automation Conf.
, pp. 145-150
-
-
Chen, L.-G.1
Jiu, J.-Y.2
Chang, H.-C.3
Lee, Y.-P.4
Ku, C.-W.5
-
19
-
-
0028561304
-
An efficient VLSI implementation of vector-radix 2-D DCT using mesh-connected 2-D array
-
June
-
K.-W. Shin, H.-W. Jeon, and Y.-S. Kang, "An efficient VLSI implementation of vector-radix 2-D DCT using mesh-connected 2-D array," in Proc. 1994 IEEE Int. Symp. Circuits and Systems, 1994, vol. 4, June 1994, pp. 47-50.
-
(1994)
Proc. 1994 IEEE Int. Symp. Circuits and Systems, 1994
, vol.4
, pp. 47-50
-
-
Shin, K.-W.1
Jeon, H.-W.2
Kang, Y.-S.3
-
20
-
-
0032072374
-
A refined fast 2-D discrete cosine transform algorithm with regular butterfly structure
-
May
-
Y.-M. Huang, J.-L. Lu, and C.-T. Hsu, "A refined fast 2-D discrete cosine transform algorithm with regular butterfly structure," IEEE Trans. Consumer Electron., vol. 44, pp. 376-383, May 1998.
-
(1998)
IEEE Trans. Consumer Electron.
, vol.44
, pp. 376-383
-
-
Huang, Y.-M.1
Lu, J.-L.2
Hsu, C.-T.3
-
21
-
-
0033872951
-
A simple processor core design for DCT/IDCT
-
Apr.
-
T.-S. Chang, C.-S. Kung, and C.-W. Jen, "A simple processor core design for DCT/IDCT," IEEE Trans. Circuits Syst. Video Technol., vol. 10, pp. 439-447, Apr. 2000.
-
(2000)
IEEE Trans. Circuits Syst. Video Technol.
, vol.10
, pp. 439-447
-
-
Chang, T.-S.1
Kung, C.-S.2
Jen, C.-W.3
-
22
-
-
0032692189
-
Cost-Effective low-power architectures of video coding systems
-
June
-
J. Chen and K. J. R. Liu, "Cost-Effective low-power architectures of video coding systems," in P roc. 1999 IEEE Int. Symp. Circuits and Systems, vol. 1, June 1999, pp. 153-156.
-
(1999)
Proc. 1999 IEEE Int. Symp. Circuits and Systems
, vol.1
, pp. 153-156
-
-
Chen, J.1
Liu, K.J.R.2
-
23
-
-
0033722127
-
Low-Power architectures for compressed domain video coding co-processor
-
June
-
_, "Low-Power architectures for compressed domain video coding co-processor," IEEE Trans. Multimedia, vol. 2, pp. 111-128, June 2000.
-
(2000)
IEEE Trans. Multimedia
, vol.2
, pp. 111-128
-
-
-
24
-
-
0030083342
-
VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications
-
Feb.
-
V. Srinivasan and K. J. R. Liu, "VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications," IEEE Trans. Circuits Syst. Video Technol., vol. 6, pp. 87-96, Feb. 1996.
-
(1996)
IEEE Trans. Circuits Syst. Video Technol.
, vol.6
, pp. 87-96
-
-
Srinivasan, V.1
Liu, K.J.R.2
-
25
-
-
0032681819
-
New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array
-
Mar.
-
S.-F. Hsiao and W.-R. Shiue, "New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array," in Proc. 1999 IEEE ICASSP, vol. 6, Mar. 1999, pp. 3517-3520.
-
(1999)
Proc. 1999 IEEE ICASSP
, vol.6
, pp. 3517-3520
-
-
Hsiao, S.-F.1
Shiue, W.-R.2
-
26
-
-
0032614261
-
A low-power IDCT macro-cell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity
-
May
-
T. Xanthopolous and A. P. Chandrakasan, "A low-power IDCT macro-cell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity," IEEE J. Solid State Circuits, vol. 34, pp. 693-703, May 1999.
-
(1999)
IEEE J. Solid State Circuits
, vol.34
, pp. 693-703
-
-
Xanthopolous, T.1
Chandrakasan, A.P.2
-
27
-
-
85013917280
-
A high-performance low-power asynchronous matrix vector multiplier for discrete cosine transform
-
Aug.
-
K. Kim and P. A. Beerel, "A high-performance low-power asynchronous matrix vector multiplier for discrete cosine transform," in Proc. First IEEE Asia Pacific Conf. ASIC's, 1999, Aug. 1999, pp. 135-138.
-
(1999)
Proc. First IEEE Asia Pacific Conf. ASIC's, 1999
, pp. 135-138
-
-
Kim, K.1
Beerel, P.A.2
-
28
-
-
0032273764
-
Power comparison of flow-graph and distributed arithmetic based DCT architectures
-
Nov.
-
M. Kuhlmann and K. K. Parhi, "Power comparison of flow-graph and distributed arithmetic based DCT architectures," in Conf. Rec. Thirty-Second Asilomar Conference on Signals, Systems & Computers, vol. 2, Nov. 1998, pp. 1214-1219.
-
(1998)
Conf. Rec. Thirty-second Asilomar Conference on Signals, Systems & Computers
, vol.2
, pp. 1214-1219
-
-
Kuhlmann, M.1
Parhi, K.K.2
-
29
-
-
0029751706
-
New architecture for high throughput-rate real-time 2-D DCT and the VLSI design
-
Sep.
-
J.-S. Chiang and H.-C. Huang, "New architecture for high throughput-rate real-time 2-D DCT and the VLSI design," in Proc. Ninth Annu. IEEE Int. ASIC Conf. Exh., Sep. 1996, pp. 219-222.
-
(1996)
Proc. Ninth Annu. IEEE Int. ASIC Conf. Exh.
, pp. 219-222
-
-
Chiang, J.-S.1
Huang, H.-C.2
-
31
-
-
0031387121
-
Performance enhancement of H.263 encoder based on zero coefficient prediction
-
Seattle, WA, Nov. 9-13
-
A. Yu, R. Lee, and M. Flynn, "Performance enhancement of H.263 encoder based on zero coefficient prediction," in Proc. ACM Conf. Multimedia '97, Seattle, WA, Nov. 9-13, 1997, pp. 21-29.
-
(1997)
Proc. ACM Conf. Multimedia '97
, pp. 21-29
-
-
Yu, A.1
Lee, R.2
Flynn, M.3
|