Evaluation of a multithreaded architecture for cellular computing

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 2002-January, Issue , 2002, Pages 311-321

  Caşcaval, Călin ^a   Castaños, José G ^a   Ceze, Luis ^a   Denneau, Monty ^a   Gupta, Manish ^a   Lieber, Derek ^a   Moreira, José E ^a   Strauss, Karin ^a   Warren, Henry S ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Bandwidth; Computer architecture; Concurrent computing; Delay; Hardware; High performance computing; Logic; Parallel processing; Silicon; Yarn

Indexed keywords

BANDWIDTH; BENCHMARKING; CACHE MEMORY; COMPUTATION THEORY; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; HARDWARE; MEMORY ARCHITECTURE; PARALLEL ARCHITECTURES; SILICON; SUPERCOMPUTERS; YARN;

CONCURRENT COMPUTING; DELAY; HIGH PERFORMANCE COMPUTING; LOGIC; PARALLEL PROCESSING;

COMPUTER ARCHITECTURE;

EID: 11844296497     PISSN: 15300897     EISSN: None     Source Type: Journal    
DOI: 10.1109/HPCA.2002.995720     Document Type: Article

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