A complementary switched MOSFET architecture for the 1/f noise reduction in linear analog CMOS ICs

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 6, 2007, Pages 1352-1361

  Koh, Jeongwook ^b,c   Schmitt Landsiedel, Doris ^a,b   Thewes, Roland ^a,d,e   Brederlow, Ralf ^a,d,f  

^a IEEE

^b TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^c SAMSUNG Electronics   (South Korea)

^d INFINEON TECHNOLOGIES AG   (Germany)

^e QIMONDA DRESDEN GMBH AND CO OHG   (Germany)

^f Texas Instruments Deutschland GmbH   (Germany)

Author keywords

1 f noise reduction; CMOS linear analog IC; Switched bias technique

Indexed keywords

CMOS INTEGRATED CIRCUITS; NOISE ABATEMENT; OPERATIONAL AMPLIFIERS; PHASE NOISE; STANDARDS;

CMOS MILLER OPERATIONAL AMPLIFIERS; DIGITAL CMOS TECHNOLOGY; SWITCHED BIAS TECHNIQUE;

MOSFET DEVICES;

EID: 34249778119     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.897144     Document Type: Article

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