A new capacitorless IT DRAM cell: Surrounding gate MOSFET with vertical channel (SGVC cell)

IEEE Transactions on Nanotechnology

Volumn 6, Issue 3, 2007, Pages 352-356

  Jeong, Hoon ^b   Song, Ki Whan ^c   Park, Il Han ^b   Kim, Tae Hun ^b   Lee, Yieun Seung ^b   Kim, Seong Goo ^c   Seo, Jun ^c   Cho, Kyoungyong ^c   Lee, Kangyoon ^c   Shin, Hyungcheol ^a,b   Lee, Jong Duk ^a,b   Park, Byung Gook ^a,b  

^a IEEE

^b Seoul National University   (South Korea)

^c SAMSUNG Electronics   (South Korea)

Author keywords

IT DRAM cell; Memory effect; Sensing margin; Surrounding gate; Vertical channel

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; MEASUREMENT THEORY; MOSFET DEVICES;

IT DRAM CELL; MEMORY EFFECT; SENSING MARGIN; SURROUNDING GATE; VERTICAL CHANNEL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 34248676040     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2007.893575     Document Type: Article

References (5)

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