Scaled 1T-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 38-39

  Ranica, R ^a   Villaret, A ^a   Malinge, P ^a   Gasiot, G ^a   Mazoyer, P ^a   Roche, P ^a   Candelier, P ^a   Jacquet, F ^a   Masson, P ^b   Bouchakour, R ^b   Fournel, R ^a   Schoellkopf, J P ^a   Skotnicki, T ^a  

^a STMICROELECTRONICS   (France)

^b AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; FORMAL LOGIC; SUBSTRATES;

EDRAM APPLICATIONS; GATE OXIDE THICKNESSES; LOGIC PROCESS;

CMOS INTEGRATED CIRCUITS;

EID: 33745149710     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469203     Document Type: Conference Paper

References (7)

1. R. Ranica et al., VLSI Tech. Dig., 2004, p. 128-9
2. S. Okhonin et al., IEEE Intl. SOI Conf., 2001, pp. 153-4
3. T. Shino et al., VLSI Tech. Dig., 2004, p. 132-3
4. C. Kuo et al., IEDM Tech. Dig., 2002, pp.843-6
5. R.Ranica et al., IEDM 2004, p.Tech. Dig., 2004, p. 277-80
6. Y. Taur, T.H. Ning, "Fundamentals of Modern VLSI devices"
7. P. Roche et al., IEEE Trans. On Nuclear Science, Vol.50, Dec. 2003.