-
2
-
-
0034461413
-
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
-
BALASUBRAMONIAN, R., ALBONESI, D., BUYUKTOSUNOGLU, A., AND DWARKADAS, S. 2000. Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. In Proceedings of the International Symposium on Microarchitecture.
-
(2000)
Proceedings of the International Symposium on Microarchitecture
-
-
Balasubramonian, R.1
Albonesi, D.2
Buyuktosunoglu, A.3
Dwarkadas, S.4
-
3
-
-
0033204190
-
Analytical modeling of set-associative cache behavior
-
HARPER, J., KERBYSON, D., AND NUDD, G. 1999. Analytical modeling of set-associative cache behavior. IEEE Trans. Comput. 48, 10 (Oct.), 1009-1024.
-
(1999)
IEEE Trans. Comput.
, vol.48
, Issue.10 OCT
, pp. 1009-1024
-
-
Harper, J.1
Kerbyson, D.2
Nudd, G.3
-
5
-
-
84858531167
-
-
INTEL PENTIUM IV. ftp://download.intel.com/design/Pentium4/manuals/ 24896609.pdf.
-
-
-
-
7
-
-
0032218621
-
Synthesis of power efficient systems-on-silicon
-
KIROVSKI, D., LEE, C., POTKONJAK, M., AND MANGIONE-SMITH, W. 1998. Synthesis of power efficient systems-on-silicon. In Proceedings of Asian South Pacific Design Automation Conference.
-
(1998)
Proceedings of Asian South Pacific Design Automation Conference
-
-
Kirovski, D.1
Lee, C.2
Potkonjak, M.3
Mangione-Smith, W.4
-
8
-
-
0032204608
-
A new direction for computer architecture research
-
KOZYRAKIS, C. AND PATTERSON, D. 1998. A new direction for computer architecture research. IEEE Comput. 31, 11 (Nov.), 24-32.
-
(1998)
IEEE Comput.
, vol.31
, Issue.11 NOV
, pp. 24-32
-
-
Kozyrakis, C.1
Patterson, D.2
-
9
-
-
84949897452
-
Efficient power estimation techniques for HW/SW systems
-
IEEE Computer Society Press, Los Alamitos, Calif
-
LAJOLO, M., RAGHUNATHAN, A., DEY, S., LAVAGNO, L., AND SANGIOVANNI-VINCENTELLI, A. 1999. Efficient power estimation techniques for HW/SW systems. In Proceedings of IEEE Alessandro Volta Memorial Workshop on Low-Power Design. IEEE Computer Society Press, Los Alamitos, Calif.
-
(1999)
Proceedings of IEEE Alessandro Volta Memorial Workshop on Low-power Design
-
-
Lajolo, M.1
Raghunathan, A.2
Dey, S.3
Lavagno, L.4
Sangiovanni-Vincentelli, A.5
-
11
-
-
0031634246
-
A framework for estimating and minimizing energy dissipation of embedded HW/SW systems
-
LI, Y. AND HENKEL, J. 1998. A framework for estimating and minimizing energy dissipation of embedded HW/SW systems. In Proceedings of the Design Automation Conference.
-
(1998)
Proceedings of the Design Automation Conference
-
-
Li, Y.1
Henkel, J.2
-
12
-
-
3042548199
-
An analytical model of locality and caching
-
Michigan State University
-
BREHOB, M. AND ENBODY, R. J. 1996. An analytical model of locality and caching. Tech. rep., Michigan State University.
-
(1996)
Tech. Rep.
-
-
Brehob, M.1
Enbody, R.J.2
-
14
-
-
0014701246
-
Evaluation techniques for storage hierarchies
-
MATTSON, R., GECSEI, J., SLUTZ, D., AND TRAIGER, I. 1970. Evaluation techniques for storage hierarchies. IBM Syst. J. 9, 2.
-
(1970)
IBM Syst. J.
, vol.9
, Issue.2
-
-
Mattson, R.1
Gecsei, J.2
Slutz, D.3
Traiger, I.4
-
15
-
-
84858529230
-
-
MOTOROLA MPC500. http://e www.motorola.com/files/platforms/doc/ref. manual/MGT560RM.pdf.
-
-
-
-
16
-
-
84858525127
-
-
MOTOROLA MPC5200. http://e www.motorola.com/files/32bit/doc/ref.manual/ G2CORERM.pdf.
-
-
-
-
17
-
-
84858525126
-
-
MOTOROLA MPC823. http://e-www.motorola.com/files/if/cnb/MPC823UM.pdf.
-
-
-
-
19
-
-
0034313231
-
Evaluating trace cache on moderate-scale processors
-
SATO, T. 2000. Evaluating trace cache on moderate-scale processors. IEEE Comput. 147,6 (Nov), 369-374.
-
(2000)
IEEE Comput.
, vol.147
, Issue.6 NOV
, pp. 369-374
-
-
Sato, T.1
-
22
-
-
0032027434
-
V830R/AV: Embedded multimedia superscalar RISC processor
-
SUZUKI, K., ARAI, T., AND KOUHEI, N. 1998. V830R/AV: Embedded multimedia superscalar RISC processor. IEEE Micro 18, 2 (Mar.), 36-47.
-
(1998)
IEEE Micro
, vol.18
, Issue.2 MAR
, pp. 36-47
-
-
Suzuki, K.1
Arai, T.2
Kouhei, N.3
-
24
-
-
0030149507
-
CACTI: An enhanced cache access and cycle time model
-
WILTON, S. AND JOUPPI, N. 1996. CACTI: An enhanced cache access and cycle time model. IEEE J. Solid State Circ. 31, 5 (May), 677-688.
-
(1996)
IEEE J. Solid State Circ.
, vol.31
, Issue.5 MAY
, pp. 677-688
-
-
Wilton, S.1
Jouppi, N.2
|