Time-energy design space exploration for multi-layer memory architectures

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 318-323

  Szymanek, Radoslaw ^a   Catthoor, Francky ^b,c   Kuchcinski, Krzysztof ^a  

^a LUND UNIVERSITY   (Sweden)

^b IMEC   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DATA ACCESS METHODS; MULTILAYER MEMORY ARCHITECTURE; RANDOM TASK GRAPHS; APPLICATION EXECUTION; DESIGN SPACE EXPLORATION; EXPLORATION ALGORITHMS; HIERARCHICAL COMPOSITION; IMAGE PROCESSING APPLICATIONS; MULTI OBJECTIVE; MULTI-LAYER MEMORY ARCHITECTURES; OPTIMAL RESULTS;

ALGORITHMS; COMPUTER ARCHITECTURE; ENERGY UTILIZATION; GRAPH THEORY; HIERARCHICAL SYSTEMS; IMAGE PROCESSING; LOGIC DESIGN; MEDICAL IMAGING; PROGRAM PROCESSORS; DESIGN; ECONOMIC AND SOCIAL EFFECTS; EXHIBITIONS; PARETO PRINCIPLE;

DATA STORAGE EQUIPMENT; MEMORY ARCHITECTURE;

EID: 3042656853     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268867     Document Type: Conference Paper

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