Pipelining of double precision floating point division and square root operations

Proceedings of the Annual Southeast Conference

Volumn 2006, Issue , 2006, Pages 488-493

  Thakkar, Anuja Jayraj ^a   Ejnioui, Abdel ^b  

^a University of Central Florida   (United States)

^b School of Interdisciplinary Global Studies   (United States)

Author keywords

Division; Floating point; FPGA; Pipelining; Square root

Indexed keywords

ARITHMETIC OPERATIONS; FLOATING POINT DIVISIONS; FLOATING POINTS; SQUARE ROOT OPERATIONS;

ALGORITHMS; COMPUTER ARCHITECTURE; DATA REDUCTION; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PRECISION ENGINEERING;

PIPELINE PROCESSING SYSTEMS;

EID: 34248327871     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1185448.1185555     Document Type: Conference Paper

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