An efficient reference frame storage scheme for H.264 HDTV decoder

2006 IEEE International Conference on Multimedia and Expo, ICME 2006 - Proceedings

Volumn 2006, Issue , 2006, Pages 361-364

  Peng, Zhang ^a   Wen, Gao ^a   Di, Wu ^a   Don, Xie ^b  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

^b Grandview Semiconductor (Beijing) Corporation   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; DECODING; HIGH DEFINITION TELEVISION; PIXELS; STORAGE ALLOCATION (COMPUTER);

MEMORY BANDWIDTH EFFICIENCY; PIXEL DUPLICATION MECHANISM; REFERENCE FRAME STORAGE;

VLSI CIRCUITS;

EID: 34247559269     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICME.2006.262511     Document Type: Conference Paper

References (8)

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2. J. L. Hennessy and D. A. Partterson, Computer Architecture: A Quantitative Approach, 3rd ed. San Francisco, CA: Morgan Kaufmann, 2002.
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4. T. Takizawa, J. Tajime, H. Harasaki, "High performance and cost effective memory architecture for an HDTV decoder LSI", Proc. of ICASSP 1999, vol. 4, pp. 1981-1984, Mar. 1999.
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7. H. Kim, I. C. Park, "High-Performance and Low-Power Memory-Interface Architecture for Video Processing Applications", IEEE trans. on CSVT, vol. 11, no. 11, Nov. 2001.
8. S. Park, Y. Yi, I. C. Park, "High Performance Memory Mode Control for HDTV Decoders", IEEE trans. on Consumer Electronics, vol. 49, no. 4, Nov. 2003.