Architecture and bus-arbitration schemes for MPEG-2 video decoder

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 9, Issue 5, 1999, Pages 727-736

  Li, Jui Hua ^b   Ling, Nam ^a,b  

^a IEEE

^b Santa Clara University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; COSINE TRANSFORMS; DECODING; DISTRIBUTED PARAMETER CONTROL SYSTEMS; DYNAMIC RANDOM ACCESS STORAGE; IMAGE COMPRESSION; MOTION COMPENSATION; REAL TIME SYSTEMS; SIGNAL FILTERING AND PREDICTION;

BIDIRECTIONALLY PREDICTED PICTURE BITSTREAM; BUS ARBITRATION SCHEMES; HIERARCHICAL CONTROLLER TECHNIQUE; INPUT OUTPUT BUFFER; MOVING PICTURE EXPERTS GROUP; VARIABLE LENGTH DECODER; VIDEO DECODER;

VIDEO SIGNAL PROCESSING;

EID: 0033350810     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.780362     Document Type: Article

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