-
2
-
-
84944408275
-
IA-32 Execution Layer: A two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems
-
IEEE, Dec
-
L. Baraz, T. Devor, O. Etzion, S. Goldenberg, A. Skaletsky, Y. Wang, and Y. Zemach. IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems. In Proceedings of the 36th International Symposium on Microarchitecture, pages 191-201. IEEE, Dec 2003.
-
(2003)
Proceedings of the 36th International Symposium on Microarchitecture
, pp. 191-201
-
-
Baraz, L.1
Devor, T.2
Etzion, O.3
Goldenberg, S.4
Skaletsky, A.5
Wang, Y.6
Zemach, Y.7
-
7
-
-
0032291406
-
An eight-issue tree VLIW processor for dynamic binary translation
-
K. Ebcioglu, J. Fritts, S. Kosonocky, M. Gschwind, E. Altman, K. Kailas, and T. Bright. An eight-issue tree VLIW processor for dynamic binary translation. In Proceedings of the 1998 IEEE International Conference on Computer Design, 1998.
-
(1998)
Proceedings of the 1998 IEEE International Conference on Computer Design
-
-
Ebcioglu, K.1
Fritts, J.2
Kosonocky, S.3
Gschwind, M.4
Altman, E.5
Kailas, K.6
Bright, T.7
-
8
-
-
0019596071
-
Trace scheduling: A technique for global microcode compaction
-
July
-
J. A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, 30(7):478-490, July 1981.
-
(1981)
IEEE Transactions on Computers
, vol.30
, Issue.7
, pp. 478-490
-
-
Fisher, J.A.1
-
9
-
-
0032667958
-
An evaluation of staged run-time optimizations in dye
-
ACM Press
-
B. Grant, M. Philipose, M. Mock, C. Chambers, and S. J. Eggers. An evaluation of staged run-time optimizations in dye. In Proceedings of the ACM SIGPLAN 1999 Conference on Programming Language Design and Implementation, pages 293-304. ACM Press, 1999.
-
(1999)
Proceedings of the ACM SIGPLAN 1999 Conference on Programming Language Design and Implementation
, pp. 293-304
-
-
Grant, B.1
Philipose, M.2
Mock, M.3
Chambers, C.4
Eggers, S.J.5
-
10
-
-
0009376728
-
Considerations in the design of hydra: A multiprocessor-on-a-chip microarchitecture
-
Technical Report CSL-TR-98-749
-
L. Hammond and K. Olukotun. Considerations in the design of hydra: A multiprocessor-on-a-chip microarchitecture. Technical Report CSL-TR-98-749, 1998.
-
(1998)
-
-
Hammond, L.1
Olukotun, K.2
-
11
-
-
27644534876
-
Hardware and software architectures for the cell processor
-
New York, NY, USA, ACM Press
-
P. Hofstee and M. Day. Hardware and software architectures for the cell processor. In CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pages 1-1, New York, NY, USA, 2005. ACM Press.
-
(2005)
CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
, pp. 1-1
-
-
Hofstee, P.1
Day, M.2
-
12
-
-
0027595384
-
The superblock: An effective technique for vliw and superscalar compilation
-
W. Hwu, S. Mahlke, W. Chen, P. Chang, N. Warter, R. Bringmann, R. Ouellette, R. Hank, T. Kiyohara, G. Haab, J. Holm, and D. Lavery. The superblock: an effective technique for vliw and superscalar compilation. The Journal of Supercamputing, 7(1-2):229-248, 1993.
-
(1993)
The Journal of Supercamputing
, vol.7
, Issue.1-2
, pp. 229-248
-
-
Hwu, W.1
Mahlke, S.2
Chen, W.3
Chang, P.4
Warter, N.5
Bringmann, R.6
Ouellette, R.7
Hank, R.8
Kiyohara, T.9
Haab, G.10
Holm, J.11
Lavery, D.12
-
13
-
-
34247357704
-
-
Program Optimization. PhD thesis, Department of Information and Computer Science, University of California, Irvine, Nov
-
T. Kistler. Continuous Program Optimization. PhD thesis, Department of Information and Computer Science, University of California, Irvine, Nov. 1999.
-
(1999)
Continuous
-
-
Kistler, T.1
-
14
-
-
0003902445
-
The technology behind Crusoe™processors
-
Technical Brief, Jan
-
A. Klaiber. The technology behind Crusoe™processors. Transmeta Technical Brief, Jan. 2000.
-
(2000)
Transmeta
-
-
Klaiber, A.1
-
15
-
-
0037702458
-
Using thread-level speculation to simplify manual parallelization
-
New York, NY, USA, ACM Press
-
M. K. Prabhu and K. Olukotun. Using thread-level speculation to simplify manual parallelization. In PPoPP '03: Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming, pages 1-12, New York, NY, USA, 2003. ACM Press.
-
(2003)
PPoPP '03: Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming
, pp. 1-12
-
-
Prabhu, M.K.1
Olukotun, K.2
-
17
-
-
0031374420
-
Trace processors
-
E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. Smith. Trace processors. In International Symposium on Microarchitecture, pages 138-148, 1997.
-
(1997)
International Symposium on Microarchitecture
, pp. 138-148
-
-
Rotenberg, E.1
Jacobson, Q.2
Sazeides, Y.3
Smith, J.4
-
19
-
-
3142766211
-
Atom: A system for building customized program analysis tools
-
A. Srivastava and A. Eustace. Atom: a system for building customized program analysis tools. SIGPLAN Not., 39(4):528-539, 2004.
-
(2004)
SIGPLAN Not
, vol.39
, Issue.4
, pp. 528-539
-
-
Srivastava, A.1
Eustace, A.2
-
20
-
-
0033344478
-
The superthreaded processor architecture
-
J.-Y. Tsai, J. Huang, C. Amlo, D. J. Lilja, and P.-C. Yew. The superthreaded processor architecture. IEEE Transactions on Computers, 48(9):881-902, 1999.
-
(1999)
IEEE Transactions on Computers
, vol.48
, Issue.9
, pp. 881-902
-
-
Tsai, J.-Y.1
Huang, J.2
Amlo, C.3
Lilja, D.J.4
Yew, P.-C.5
-
21
-
-
0034819518
-
High-level adaptive program optimization with ADAPT
-
July
-
M. J. Voss and R. Eigemann. High-level adaptive program optimization with ADAPT. ACM SIGPLAN Notices, 36(7):93-102, July 2001.
-
(2001)
ACM SIGPLAN Notices
, vol.36
, Issue.7
, pp. 93-102
-
-
Voss, M.J.1
Eigemann, R.2
|