A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2006, Issue , 2006, Pages 61-66

  Fujiwara, Hidehiro ^a   Nii, Koji ^a   Miyakoshi, Junichi ^a   Murachi, Yuichiro ^a   Morita, Yasuhiro ^b   Kawaguchi, Hiroshi ^a   Yoshimoto, Masahiko ^a  

^a KOBE UNIVERSITY   (Japan)

^b KANAZAWA UNIVERSITY   (Japan)

Author keywords

Data bit reordering; Low power SRAM; Majority logic; Real time image processing; Two port SRAM

Indexed keywords

DATA RECORDING; ELECTRIC POWER UTILIZATION; ENERGY CONSERVATION; MAJORITY LOGIC; PROBABILITY; REAL TIME SYSTEMS;

DATA-BIT REORDERING; LOW POWER SRAM; REAL-TIME IMAGE PROCESSING;

TELEVISION EQUIPMENT;

EID: 34247199959     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1165573.1165589     Document Type: Conference Paper

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