Minimizing spurious switching activities with transistor sizing

VLSI Design

Volumn 15, Issue 2, 2002, Pages 537-545

  Wróblewski, Artur ^a   Schimpfle, Christian V ^b   Schumacher, Otto ^c   Nossek, Josef A ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b Texas Instruments Deutschland GmbH   (Germany)

^c INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

CMOS; Glitches; Low power; Transistor sizing; VLSI

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC GATES; SIGNAL PROCESSING; SWITCHING THEORY; VLSI CIRCUITS;

GLITCHES; TRANSISTOR SIZING;

MOSFET DEVICES;

EID: 0036763047     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1080/1065514021000012156     Document Type: Article

References (7)

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