Low thermal budget processing for sequential 3-D IC fabrication

IEEE Transactions on Electron Devices

Volumn 54, Issue 4, 2007, Pages 707-714

  Rajendran, Bipin ^a,b   Shenoy, Rohit S ^c   Witte, Daniel J ^a   Chokshi, Nehal S ^d,e   DeLeon, Robert L ^d,f   Tompa, Gary S ^d,g   Pease, R Fabian W ^a  

^a Stanford University   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM ALMADEN RESEARCH CENTER   (United States)

^d AMBP Tech Corporation   (United States)

^e Thomas Weisel Partners LLC   (United States)

^f UNIVERSITY AT BUFFALO   (United States)

^g STRUCTURED MATERIALS INDUSTRIES INC   (United States)

Author keywords

CMOSFET; Integrated circuit fabrication; Laser annealing; Low pressure chemical vapor deposition (LPCVD)

Indexed keywords

ANNEALING; DOPING (ADDITIVES); FABRICATION; FIELD EFFECT TRANSISTORS; LASER APPLICATIONS; LOW PRESSURE CHEMICAL VAPOR DEPOSITION;

CMOS FIELD EFFECT TRANSISTOR; LASER ANNEALING;

CMOS INTEGRATED CIRCUITS;

EID: 34147117601     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.891300     Document Type: Article

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