The multiple-gate MOS-JFET transistor

International Journal of High Speed Electronics and Systems

Volumn 12, Issue 2, 2002, Pages 511-520

  Blalock, Benjamin J ^a   Cristoloveanu, Sorin ^b   Dufrene, Brian M ^c   Allibert, F ^b   Mojarradi, Mohammad M ^d  

^a University of Tennessee Knoxville   (United States)

^b Grenoble INP Phelma   (France)

^c MISSISSIPPI STATE UNIVERSITY   (United States)

^d CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTIVITY; ELECTRIC INSULATORS; GATES (TRANSISTOR); LOGIC GATES; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; SILICON;

CONDUCTION CONTROL; SINGLE TRANSISTORS;

MOSFET DEVICES;

EID: 0142207316     PISSN: 01291564     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0129156402001423     Document Type: Conference Paper

References (2)

1. S. Cristoloveanu, T. Ernst, D. Munteanu and T. Ouisse, "Ultimate MOSFETs on SOI: ultra-thin, single gate, double gate, or ground plane," Int. J. of High Speed Electronics and Systems, WOFE'99, vol. 10, no. 1, pp. 217-230, 2000.
2. K. W. Golke and P. S. Fechner, "Integrated Circuit Impedance Device and Method of Manufacture Therefor," U.S. Patent 6 180 984, Jan. 30, 2001.