Temperature-compensated reference circuits for SOI

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 112-114

  Terry, S C ^a   Chen, S ^a   Blalock, B J ^a   Jackson, J R ^a   Dufrene, B M ^a,b   Mojarradi, M M ^c   Islam, S K ^a   Ericson, M N ^d  

^a UNIVERSITY OF TENNESSEE   (United States)

^b IBM   (United States)

^c CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^d OAK RIDGE NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARORA MODEL; FOUR GATE TRANSISTORS; STANDARD BANDGAP ARCHITECTURE; TEMPERATURE-COMPENSATED REFERENCE CIRCUITS;

CMOS INTEGRATED CIRCUITS; ELECTRIC CHARGE; ELECTRIC CURRENTS; JUNCTION GATE FIELD EFFECT TRANSISTORS; MATHEMATICAL MODELS; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; TEMPERATURE CONTROL; VOLTAGE CONTROL;

SILICON ON INSULATOR TECHNOLOGY;

EID: 16244384965     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. B. J. Blalock, S. Cristoloveanu, B. M. Dufrene, and M. M. Mojorradi, "The multiple-gate MOS-JFET," Int. J. of High-Speed Electronics and Systems, vol. 12, no. 2, pp. 511-520, 2002.
2. D. F. Bower and L. C. Tippie, "Junction field effect voltage reference," U.S. Patent, Patent No. 5,973,559, Oct. 26, 1999.
3. B. Dufrene, K. Akarvardar, S. Cristoloveanu, B. J. Blalock, P. Gentil, E. Kolawa, M. M. Mojarradi, "Investigation of the four gate action in G4-FETs," to be published in the November 2004 issue of IEEE Trans. on Electron Devices.
4. W. M. Sansen, F. O. Eynde, and M. Steyaert, "A CMOS temperature-compensated current reference," IEEE J. Solid-State Circuits, vol. 23, no. 3, pp. 821-824, 1988.
5. H. J Oguey and D. Aebischer, "CMOS current reference without resistance," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1132-1135, 1997.
6. E. Vittoz and J. Fellrath, "CMOS analog circuits based on weak inversion operation," IEEE J. Solid-State Circuits, vol. SC-12, pp. 224-231, June 1977.
7. N. D. Arora, J. R. Hauser, and D. J. Roulston, "Electron and hole mobilities in Silicon as a function of concentration and temperature," IEEE Tran. On Electron Devices, vol. ED-29, no. 2, pp. 292-295, February 1982.