Power/performance hardware optimization for synchronization intensive applications in MPSoCs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Monchiero, Matteo ^a   Palermo, Gianluca ^a   Silvano, Cristina ^a   Villa, Oreste ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; ENERGY CONSERVATION; OPTIMIZATION; SYNCHRONIZATION; SYSTEMS ANALYSIS;

PERFORMANCE OPTIMIZATION; SPIN LOCKS; SYNCHRONIZATION-OPERATION BUFFER;

MICROPROCESSOR CHIPS;

EID: 34047168042     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.243994     Document Type: Conference Paper

References (22)

1. http://www-flash.stanford.edu/apps/SPLASH/.
2. STMicroelectronics industrial data.
3. B. Ackland, A. Anesko, D. Brinthaupt, S. Daubert, A. Kalavade, J. Knobloch, E. Micca, M. Moturi, C. Nicol, J. O'Neill, J. Othmer, E. Sckinger, K. Singh, J. Sweet, and C. Terman. A Single-Chip 1.6 Billion 16-b MAC/s Multiprocessor DSP. IEEE JSSC, March 2000.
4. S. Adve and K. Gharachorloo. Shared memory consistency models: A tutorial. Technical Report 95/7, WRL, 1995.
5. T. Anderson. The performance of of spin lock alternatives for shared memory multiprocessors. IEEE Trans. on Parallel and Distributed Systems, January 1990.
6. E. Artiaga, N. Navarro, X. Martorell, and Y. Becerra. Implementing PARMACS macros for shared-memory multiprocessor environments. Technical Report UPC-DAC-1997-07, UPC-DAC, 1997.
7. A. Beda, N. Gatti, and F. Amigoni. Heart-rate pacing simulation and control via multiagent systems. In Proc. of Agents Applied in Health Care, 2004.
8. S. Dutta, R. Jensen, and A. Rieckmann. Viper: A multiprocessor SOC for advanced set-top box and digital tv systems. IEEE Design & Test of Computers, September/October 2001.
9. A. Kagi, D. Burger, and J. R. Goodman. Efficient synchronization: let them eat QOLB. In Proc. of ISCA, 1997.
10. P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded Spare processor. IEEE Micro, pages 2129, March/April 2005.
11. M. Loghi and M. Poncino. Exploring energy/performance tradeoffs in shared memory MPSoC: Snoop-based cache coherence vs. software solutions. In Proc. of DATE, 2005.
12. C. McNairy and R. Bhatia. Montecito: A dual-core, dual-thread Itanium processor. IEEE Micro, pages 10-20, March/April 2005.
13. J. M. Mellor-Crummey and M. L. Scott. Algorithms for scalable synchronization on shared-memory multiprocessors. ACM Trans. on Computer Systems, 9(1):21-65, 1991.
14. T. Mudge. Power: A First Class Constraint for Future Architectures. In HPCA-6, 2000.
15. G. Palermo and C. Silvano. PIRATE: A Framework for Power/Performance Exploration of Network-On-Chip Architectures. In Proc. of PATMOS, 2004.
16. D. A. Patterson and J. L. Hennessy. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 2003.
17. P. Paulin, C. Pilkington, M. Langevin, E. Bensoudane, and G. Nicolescu. Parallel programming models for a multiprocessor SoC platform applied to high-speed traffic management. In Proc. of CODES-ISSS, pages 48-53, 2004.
18. W. Qin and S. Malik. Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. In Proc. of DATE, 2003.
19. R. Rajwar and J. Goodman. Transactional execution: Toward reliable, high-performance multithreading. IEEE MICRO, November/December 2003.
20. A. Sinha, N. Ickes, and A. Chandrakasan. Instruction level and operating system profiling for energy exposed software. IEEE Trans. on VLSI, 11(6), December 2003.
21. W. Wolf. The future of multiprocessor systems-on-chips. In Proc. of DAC, 2004.
22. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In Proc. of ISCA, 1995.