Profile guided selection of ARM and Thumb instructions

Joint COnference on Languages, Compilers and Tools for Embedded Systems and Software and Compilers for Embedded Systems

Volumn , Issue , 2002, Pages 56-64

  Krishnaswamy, Arvind ^a   Gupta, Rajiv ^a  

^a University of Arizona   (United States)

Author keywords

16 32 bit instructions; Code size and speed; Low power

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); ENERGY UTILIZATION; PROGRAM PROCESSORS;

THUMB INSTRUCTION SETS;

EMBEDDED SYSTEMS;

EID: 0036977342     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/513829.513840     Document Type: Conference Paper

References (12)

1. D. Burger and T.M. Austin, "The Simplescalar Tool Set, Version 2.0," Computer Architecture News, pages 13-25, June 1997.
2. S. Furber, "ARM system Architecture," Publisher: Addison Wesley Longman, 1996.
3. S. Gurumurthi, A. Sivasubramaniam, M.J. Irwin, N. Vijaykrishnan, and M. Kandemir, "Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach," The Eight International Symposium on High Performance Computer Architecture (HPCA-8), Feb. 2002.
4. "SA-110 Microprocessor Technical Reference Manual," ftp://download.intel.com/design/strong/applnots/ 27819401.pdf.
5. "The Intel XScale Microarchitecture Technical Summary," ftp://download.intel.com/design/intelxscale/ XScaleDatasheet4.pdf.
6. J. Johnston, Maintainer, Newlib http://sources.redhat.com/newlib/.
7. C. Lee, M. Potkonjak, and W.H. Mangione-Smith, "Mediabench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems," IEEE/ACM International Symposium on Microarchitecture (MICRO), Research Triangle Park, North Carolina, December 1997.
8. MIPS Technologies, "MIPS32 Architecture for Programmers Volume IV-a: The MIPS16 Application Specific Extension to the MIPS32 Architecture," March 2001.
9. G. Reinman and N. Jouppi, "An Integrated Cache Timing and Power Model," Technique Report, Western Research Lab., 1999.
10. rebel.com, Netwinder Family, http://www.rebel.com/netwinder.
11. D. Seal, Editor, "ARM Architecture Reference Manual," Second Addition, Addison-Wesley.
12. S. Wilton and N.Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," Technique Report, Western Research Lab., May 93.