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Volumn 54, Issue 2, 2007, Pages 200-204

A multiwindow partial buffering scheme for FPGA-based 2-D convolvers

Author keywords

Field programmable gate arrays (FPGAs); full buffering (FB); multiwindow (MW); partial buffering (PB); two dimensional (2 D) convolution

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; CONVOLUTIONAL CODES; IMAGE PROCESSING;

EID: 33947574350     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.886898     Document Type: Article
Times cited : (55)

References (7)
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    • (1999) IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol.7 , Issue.3 , pp. 229-308
    • Bosi, B.1    Bois, G.2    Savaria, Y.3
  • 4
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    • A high-performance fully reconfigurable FPGA-based 2-D convolution processor
    • S. Perri, M. Lanuzza, P. Corsonello, and G. Cocorullo, “A high-performance fully reconfigurable FPGA-based 2-D convolution processor,” Microprocess. Microsyst., vol. 29, pp. 381–391, 2005.
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    • Data buffering and allocation in mapping generalized template matching on reconfigurable systems
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    • Liang, X.1    Jean, J.S.N.2    Tomko, K.3
  • 6
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    • Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing
    • Feb.
    • F. Cardells-Tormo and P. Molinet, “Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing,” IEEE Trans. Circuits. Syst. II: Exp. Briefs, vol. 53, no. 2, pp. 105–109, Feb. 2006.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.