A high-performance fully reconfigurable FPGA-based 2D convolution processor

Microprocessors and Microsystems

Volumn 29, Issue 8-9, 2005, Pages 381-391

  Perri, Stefania ^a   Lanuzza, Marco ^a   Corsonello, Pasquale ^a,b   Cocorullo, Giuseppe ^a  

^a UNIVERSITY OF CALABRIA   (Italy)

^b UNIVERSITY MEDITERRANEA OF REGGIO CALABRIA   (Italy)

Author keywords

Convolution; Image processing; Single instruction multiple data circuits

Indexed keywords

CONVOLUTION; IMAGE PROCESSING; OPTIMIZATION; PROGRAM PROCESSORS; REAL TIME SYSTEMS;

SINGLE INSTRUCTION MULTIPLE DATA CIRCUITS; TIME-CONSUMING RECONFIGURATION; VIDEO PROCESSORS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 24144474649     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2004.10.004     Document Type: Article

References (13)

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