Design and complexity optimization of a new digital IF for software radio receivers with prescribed output accuracy

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 2, 2007, Pages 351-366

  Chan, S C ^a   Tsui, K M ^a   Yeung, K S ^a   Yuk, T I ^a  

^a UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Design and multiplier less realization; Prescribed output accuracy; Sampling rate conversion; Software radio receiver (SRR); Variable digital filters (VDFs); Wordlength determination

Indexed keywords

DESIGN; DIGITAL FILTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LAGRANGE MULTIPLIERS; OPTIMIZATION;

DIGITAL INTERMEDIATE FREQUENCY; MARGINAL ANALYSIS METHOD; SAMPLING RATE CONVERSION; SOFTWARE RADIO RECEIVERS;

RADIO RECEIVERS;

EID: 33947424823     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.886003     Document Type: Article

References (37)

1. T. Hentschel and G. Fettweis, "Sample rate conversion for software radio," IEEE Commun. Mag., pp. 142-150, Aug. 2000.
2. C. Y. Fung and S. C. Chan, "A multistage filterbank-based channelizer for software radio base stations," in Proc. IEEE Int. Symp. on Circuits Syst. (ISCAS), 2002, vol. 3, pp. 429-432.
3. R. H. Walden, "Performance trends for analog-to-digital converters," IEEE Commun. Mag., vol. 37, no. 2, pp. 96-101, Feb. 1999.
4. S. K. Mitra, Digital Signal Processing: A Computer-Based Approach. Singapore: McGraw-Hill, 1998.
5. H. J. Oh, S. Kim, G. Choi, and Y. H. Lee, "On the use of interpolated second-order polynomials for efficient filter design in programmable downconversion," IEEE J. Select. Areas Commun., vol. 17, no. 4, pp. 551-560, Apr. 1999.
6. A. Y. Kwentus, Z. Jiang, and A. N. Willson, "Application of filter sharpening to cascaded integrator-comb decimation filters," IEEE Trans. Signal Process., vol. 45, no. 2, pp. 457-467, Feb. 1997.
7. K. S. Yeung and S. C. Chan, "On the design and multiplier-less realization of digital IF for software radio receivers," in Proc. XI Eur. Signal Proces. Conf. (EUSIPCO), Toulouse, France, Sep. 3-6, 2002, vol. 1, pp. 695-698.
8. S. C. Chan and K. S. Yeung, "On the design and multiplier-less realization of digital IF for software radio receivers with prescribed output accuracy," in Proc. 14th Int. Conf. on Digital Signal Process. (DSP), Hellas, Greece, Jul. 1-3, 2002, vol. 1, pp. 277-280.
9. C. W. Farrow, "A continuously variable digital delay element," in Proc. IEEE Int. Symp. on Circuits Syst. (ISCAS), 1988, pp. 2641-2645.
10. K. S. Yeung and S. C. Chan, "The design and multiplier-less realization of software radio receivers with reduced system delay," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 2444-2459, Dec. 2004.
11. Y. C. Lim and S. R. Parker, "FIR filter design over a discrete power-of-two coefficient space," IEEE Trans. Acoust. Speech, Signal Process., vol. 31, no. 4, pp. 583-591, Apr. 1983.
12. C. K. S. Pun, Y. C. Wu, S. C. Chan, and K. L. Ho, "An efficient design of fractional-delay digital FIR filter using farrow structure," in Proc. 11th IEEE Signal Processing Workshop on Statistical Signal Process., 2001, pp. 595-598.
13. Y. C. Lim, R. Yang, D. Li, and J. Song, "Signed power-of-two term allocation scheme for the design of digital filters," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 5, pp. 577-584, May 1999.
14. A. G. Dempster and M. D. MacLeod, "Use of minimum-adder multiplier blocks in FIR digital filters," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 9, pp. 569-577, Sep. 1995.
15. G. A. Constantinides, P. Y. K. Cheung, and W. Luk, "Wordlength optimization for linear digital signal processing," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 10, pp. 1432-1442, Oct. 2003.
16. R. Fletcher, Practical Methods of Optimization, 2nd ed. Chichester, U.K.: Wiley, 1987.
17. P. D. Fiore and L. Lee, "Closed-form and real-time wordlength adaptation," in Proc. IEEE ICASSP, 1999, vol. 5, pp. 1897-1990.
18. A. Segal, "Bit allocation and encoding of vector resource," IEEE Trans. Inf. Theory, vol. 22, no. 4, pp. 162-169, Mar. 1976.
19. B. Fox, "Discrete optimization via marginal analysis," Manag. Sci., vol. 13, pp. 210-216, Nov. 1966.
20. S. W. Wu and A. Gersho, "Rate-constrained picture-adaptive quantization for JPEG baseline coders," in Proc. IEEE ICASSP, 1993, vol. 5, pp. 390-392.
21. K. C. Zangi and R. Koilpillai, "Software radio issues in cellular base stations," IEEE J. Select. Areas Commun., vol. 17, no. 4, pp. 561-573, Apr. 1999.
22. R. E. Crochiere and L. R. Rabiner, Multirate Digital Signal Processing. Englewood Cliffs, N.J.: Prentice-Hall, 1983.
23. K. Y. Khoo, Z. Yu, and A. N. Willson, "Efficient high-speed cic decimation filter," in Proc. 11th Annu. IEEE Int. Conf. ASIC, 1998, pp. 251-254.
24. P. P. Vaidyanathan, Multirate Systems and Filter Banks. Englewood Cliffs, NJ: Prentice-Hall, 1993.
25. T. A. Ramstad, "Digital methods for conversion between arbitrary sampling frequencies," IEEE Trans. Acoust. Speech, Signal Process., vol. ASSP-32, no. 3, pp. 577-591, Jun. 1984.
26. G. S. Liu and C. H. Wei, "Programmable fractional sample delay filter with lagrange interpolation," Electron. Lett., vol. 26, no. 19, pp. 1608-1610, Sep. 1990.
27. J. M. de Carvalho and J. V. Hanson, "Efficient sample rate conversion with cubic splines," in Proc. Telecomm. Symp., 1990, pp. 439-442.
28. W. S. Lu and T. B. Deng, "An improved weighted least-squares design for variable fractional delay FIR filters," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 8, pp. 1035-1040, Aug. 1999.
29. C. K. S. Pun, S. C. Chan, K. S. Yeung, and K. L. Ho, "On the design and implementation of FIR and IIR digital filters with variable frequency characteristics," in Proc. IEEE Int. Symp. on Circuits Syst. (ISCAS) 2002, vol. 2, pp. 185-188.
30. A. Mehrotra, Cellular Radio: Analog and Digital Systems. Natick, MA: Artech House, 1994.
31. S. C. Chan and K. M. Tsui, "Multiplier-less real-valued FFT-like transformation (ML-RFFT) and related real-valued transformations," in Proc. IEEE Int. Symp. on Circuits Syst. (ISCAS), May 25-28, 2003, vol. 4, pp. 257-260.
32. K. M. Tsui and S. C. Chan, "Error analysis and efficient realization of the multiplier-less FFT-like transformation (ML-FFT) and related sinusoidal transformations," J. VLSI Signal Process., vol. 44, no. 1-2, pp. 97-115, Aug. 2006.
33. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1989.
34. T. Ojanpera and R. Prasad, WCDMA: Towards IP Mobility and Mobile Internet. Natick, MA: Artech House, 2001.
35. ETSI HIPERLAN/2 Standard, [Online]. Available: http://www.etsi.org/ technicalactiv/Hiperlan/hiperlan2.htm
36. Altera Corporation [Online]. Available: http://www.altera.com
37. S. C. Chan and K. M. Tsui, "Wordlength determination algorithms for hardware implementation of linear time-invariant systems with prescribed output accuracy," in Proc. IEEE Int. Symp. on Circuits Syst. (ISCAS) Kobe, Japan, May 23-26, 2005, pp. 2607-2610.